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1. 发明授权

US06941391B2 Fencepost descriptor caching mechanism and method therefor 有权
标题翻译：栅栏描述符缓存机制及方法
公开(公告)号：US06941391B2
公开(公告)日：2005-09-06
申请号：US10758379
申请日：2004-01-15
申请人： Christian D. Kasper
发明人： Christian D. Kasper
IPC分类号： G06F3/00 , G06F13/28 , H04L12/56
CPC分类号： H04L49/254 , G06F13/28 , H04L49/103 , H04L49/90 , H04L49/901
摘要： A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve/lookahead descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.
摘要翻译：用于减少fencepost缓冲中的传输延迟的系统和方法要求在主机和具有共享存储器的网络控制器之间提供高速缓存。高速缓存被分为具有顶部高速缓存和底部高速缓存的双缓存。从共享存储器获取第一和第二描述符地址位置。两个描述符彼此区分在于第一描述符地址位置是活动描述符的位置，第二描述符地址位置是保留/前视描述符的位置。活动描述符被复制到顶层缓存。向DMA发送命令以传送活动描述符。然后将第二描述符地址位置复制到第一描述符地址中。然后从外部存储器获取下一个描述符地址位置并将其放置在第二个描述符地址位置。

2. 发明授权

US06717910B1 Method and apparatus for controlling network data congestion 有权
公开(公告)号：US06717910B1
公开(公告)日：2004-04-06
申请号：US09163819
申请日：1998-09-30
申请人： Christian D. Kasper , Elmer H. Guritz
发明人： Christian D. Kasper , Elmer H. Guritz
IPC分类号： G06F1100
CPC分类号： H04L47/30 , H04L47/10 , H04L47/12 , H04L49/90 , H04L49/9068 , H04L49/9078
摘要： A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

3. 发明授权

US06526451B2 Method and network device for creating circular queue structures in shared memory 有权
标题翻译：用于在共享存储器中创建循环队列结构的方法和网络设备
公开(公告)号：US06526451B2
公开(公告)日：2003-02-25
申请号：US09163953
申请日：1998-09-30
申请人： Christian D. Kasper
发明人： Christian D. Kasper
IPC分类号： G06F1516
CPC分类号： H04L49/901 , G06F5/065 , H04L49/90
摘要： A method and device of creating one or more buffer structures in a shared memory that exists between a host and a network device is disclosed. The method includes the step of storing within a block of shared memory an administration block having a base address and a descriptor ring parameter, which includes information relating to a descriptor ring and frame data buffer sizes. The base address of the administration block is written into the network device. An initialization command is then issued from the host to the network device. The network device reads the administration block and shared memory and one or more descriptors are constructed within the network device. Each descriptor points to a frame data buffer within shared memory. The descriptors are then stored.
摘要翻译：公开了一种在主机和网络设备之间存在的共享存储器中创建一个或多个缓冲结构的方法和设备。该方法包括在共享存储器块中存储具有基地址和描述符环参数的管理块的步骤，其包括与描述符环和帧数据缓冲器大小有关的信息。管理块的基地址写入网络设备。然后，从主机向网络设备发出初始化命令。网络设备读取管理块和共享存储器，并且在网络设备内构建一个或多个描述符。每个描述符指向共享存储器内的帧数据缓冲区。然后存储描述符。

4. 再颁专利

USRE45278E1 Method and apparatus for changing microcode to be executed in a processor 有权
标题翻译：用于改变要在处理器中执行的微代码的方法和装置
公开(公告)号：USRE45278E1
公开(公告)日：2014-12-02
申请号：US12914978
申请日：2010-10-28
申请人： Christian D. Kasper
发明人： Christian D. Kasper
IPC分类号： G06F9/45
CPC分类号： G06F9/3017 , G06F9/268 , G06F9/328
摘要： A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control flags, executable instruction codes, and tag information. In the event that a comparison against the current program counter succeeds, then execution is altered as required per the control flags. If no comparison match is made, then execution of the instruction that was accessed by the program counter is executed.
摘要翻译：中央处理单元（CPU）热补丁电路将运行时指令流与内部高速缓存进行比较。内部高速缓存存储具有关联控制标志，可执行指令代码和标签信息的嵌入式存储器地址。如果与当前程序计数器的比较成功，则根据控制标志的要求更改执行。如果不进行比较匹配，则执行由程序计数器访问的指令。

5. 发明授权

US06356962B1 Network device and method of controlling flow of data arranged in frames in a data-based network 有权
标题翻译：网络设备和控制在基于数据的网络中以帧布置的数据流的方法
公开(公告)号：US06356962B1
公开(公告)日：2002-03-12
申请号：US09163772
申请日：1998-09-30
申请人： Christian D. Kasper
发明人： Christian D. Kasper
IPC分类号： G06F1314
CPC分类号： G06F13/128 , H04L47/10 , H04L47/29 , H04L47/30 , H04L49/90 , H04L49/901 , H04L49/9078
摘要： A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.
摘要翻译：在FIFO存储器中使用先行水印公开了一种方法和网络设备。根据本发明，当FIFO存储器中的数据已经越过水印阈值时，从FIFO存储器产生水印中断。数据脉冲串通过直接存储器存取单元传送到FIFO存储器。在FIFO存储器处检查先行水印标志，以确定FIFO存储器内是否有足够的存储器空间用于附加数据脉冲串，当先行水印标志指示时，通过直接存储器访问单元传送到FIFO存储器有足够的内存空间可用。

6. 发明授权

US06715002B2 Watermark for additional data burst into buffer memory 有权
标题翻译：用于附加数据的水印突发到缓冲存储器中
公开(公告)号：US06715002B2
公开(公告)日：2004-03-30
申请号：US10005509
申请日：2001-12-04
申请人： Christian D. Kasper
发明人： Christian D. Kasper
IPC分类号： G06F1320
CPC分类号： G06F13/128 , H04L47/10 , H04L47/29 , H04L47/30 , H04L49/90 , H04L49/901 , H04L49/9078
摘要： A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.
摘要翻译：在FIFO存储器中使用先行水印公开了一种方法和网络设备。根据本发明，当FIFO存储器中的数据已经越过水印阈值时，从FIFO存储器产生水印中断。数据脉冲串通过直接存储器存取单元传送到FIFO存储器。在FIFO存储器处检查先行水印标志，以确定FIFO存储器内是否有足够的存储器空间用于附加数据脉冲串，当先行水印标志指示时，通过直接存储器访问单元传送到FIFO存储器有足够的内存空间可用。

7. 发明授权

US07444630B2 Method and apparatus for changing microcode to be executed in a processor 有权
标题翻译：用于改变要在处理器中执行的微代码的方法和装置
公开(公告)号：US07444630B2
公开(公告)日：2008-10-28
申请号：US10774994
申请日：2004-02-09
申请人： Christian D. Kasper
发明人： Christian D. Kasper
IPC分类号： G06F9/445 , G11C15/00
CPC分类号： G06F9/3017 , G06F9/268 , G06F9/328
摘要： A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control flags, executable instruction codes, and tag information. In the event that a comparison against the current program counter succeeds, then execution is altered as required per the control flags. If no comparison match is made, then execution of the instruction that was accessed by the program counter is executed.
摘要翻译：中央处理单元（CPU）热补丁电路将运行时指令流与内部高速缓存进行比较。内部高速缓存存储具有关联控制标志，可执行指令代码和标签信息的嵌入式存储器地址。如果与当前程序计数器的比较成功，则根据控制标志的要求更改执行。如果不进行比较匹配，则执行由程序计数器访问的指令。

8. 发明授权

US07337253B2 Method and system of routing network-based data using frame address notification 有权
标题翻译：使用帧地址通知路由基于网络的数据的方法和系统
公开(公告)号：US07337253B2
公开(公告)日：2008-02-26
申请号：US11386323
申请日：2006-03-22
申请人： Christian D. Kasper
发明人： Christian D. Kasper
IPC分类号： G06F13/24 , H04L12/56 , H04L12/28 , G06F13/368
CPC分类号： H04L49/9021 , H04L49/103 , H04L49/25 , H04L49/254 , H04L49/3009 , H04L49/90 , H04L49/9031 , H04L49/9047 , H04L49/9063 , H04L49/9068
摘要： A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, working in conjunction with the host processor, receives data, including any preselected address fields. The network device includes a plurality of ports. Each port includes a FIFO receive memory for receiving at least a first portion of a frame. The first portion of the frame includes data having the preselected address fields. A direct memory access unit transfers a burst of data from the FIFO receive memory to the shared system memory. A communications processor selects the amount of data to be transferred from the FIFO receive memory based on the desired address fields to be analyzed by the host processor.
摘要翻译：公开了一种用于路由布置在帧中的基于网络的数据的方法和系统。主机处理器分析传输的数据突发，并发起一个地址和查找算法，用于将帧发送到所需的目的地。存在于与主处理器结合工作的网络设备（例如，HDLC控制器）之间的共享系统存储器接收包括任何预先选择的地址字段的数据。网络设备包括多个端口。每个端口包括用于接收帧的至少第一部分的FIFO接收存储器。帧的第一部分包括具有预选地址字段的数据。直接存储器访问单元将数据从FIFO接收存储器传送到共享系统存储器。通信处理器基于要由主处理器分析的期望的地址字段来选择要从FIFO接收存储器传送的数据量。

9. 发明授权

US07072294B2 Method and apparatus for controlling network data congestion 有权
标题翻译：控制网络数据拥塞的方法和装置
公开(公告)号：US07072294B2
公开(公告)日：2006-07-04
申请号：US10785372
申请日：2004-02-24
申请人： Christian D. Kasper , Elmer H. Guritz
发明人： Christian D. Kasper , Elmer H. Guritz
IPC分类号： H04J1/16
CPC分类号： H04L47/30 , H04L47/10 , H04L47/12 , H04L49/90 , H04L49/9068 , H04L49/9078
摘要： A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.
摘要翻译：公开了一种用于控制以帧布置并最小化拥塞的网络数据流的方法，装置和网络设备。在接收FIFO存储器内产生指示接收FIFO存储器内的帧溢出的状态错误指示符。响应于状态错误指示器，向主处理器产生指示在接收FIFO存储器内发生帧溢出的早期拥塞中断。通过增加直接存储器访问（DMA）单元突发大小的字数或修改其他活动进程的时间片之一，丢弃输入帧并接收帧的服务增强。

10. 发明授权

US06691178B1 Fencepost descriptor caching mechanism and method therefor 有权
标题翻译：栅栏描述符缓存机制及方法
公开(公告)号：US06691178B1
公开(公告)日：2004-02-10
申请号：US09510387
申请日：2000-02-22
申请人： Christian D. Kasper
发明人： Christian D. Kasper
IPC分类号： G06F1328
CPC分类号： H04L49/254 , G06F13/28 , H04L49/103 , H04L49/90 , H04L49/901
摘要： A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve/lookahead descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.
摘要翻译：用于减少fencepost缓冲中的传输延迟的系统和方法要求在主机和具有共享存储器的网络控制器之间提供高速缓存。高速缓存被分为具有顶部高速缓存和底部高速缓存的双缓存。从共享存储器获取第一和第二描述符地址位置。两个描述符彼此区分在于第一描述符地址位置是活动描述符的位置，第二描述符地址位置是保留/前视描述符的位置。活动描述符被复制到顶层缓存。向DMA发送命令以传送活动描述符。然后将第二描述符地址位置复制到第一描述符地址中。然后从外部存储器获取下一个描述符地址位置并将其放置在第二个描述符地址位置。

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