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1. 发明申请

US20130332922A1 SOFTWARE HANDLING OF HARDWARE ERROR HANDLING IN HYPERVISOR-BASED SYSTEMS 有权
标题翻译：基于超声波系统的硬件错误处理的软件处理
公开(公告)号：US20130332922A1
公开(公告)日：2013-12-12
申请号：US13493023
申请日：2012-06-11
申请人： Mehdi Entezari , Edward T. Cavanagh, JR. , Bryan E. Thompson
发明人： Mehdi Entezari , Edward T. Cavanagh, JR. , Bryan E. Thompson
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45579 , G06F2009/45587
摘要： Errors occurring on a hardware bus of a hypervisor-based system may be handled in software monitors in the hypervisor-based system. When an error occurs, guest partitions on the hypervisor-based system may be notified of the error through a monitor executing in each guest partition. Only guest partitions affected by the error may be shut down or provided other instructions for taking an action in response to the error.
摘要翻译：在基于虚拟机管理程序的系统的硬件总线上发生的错误可以在基于管理程序的系统中的软件监视器中处理。当发生错误时，可以通过在每个客户机分区中执行的监视器通知基于虚拟机管理程序的系统上的客户机分区错误。只有受该错误影响的客户机分区可能会被关闭或提供其他指令来采取行动来应对错误。

2. 发明授权

US07650443B1 Methods and apparatus for allocating access to a host device buffer 有权
标题翻译：用于分配对主机设备缓冲区的访问的方法和装置
公开(公告)号：US07650443B1
公开(公告)日：2010-01-19
申请号：US10896562
申请日：2004-07-22
申请人： Edward T. Cavanagh, Jr. , William Oldham
发明人： Edward T. Cavanagh, Jr. , William Oldham
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/4059
摘要： Methods and apparatus for allocating access to a buffer of a host device to buffer data transferred between a controller of the host device and one or more remote devices are disclosed. The host device is configured to couple to each of the one or more remote devices through one or more corresponding dedicated lanes. Buffer access is allocated by determining, for each of one or more remote devices coupled to the host device, a number of dedicated lanes between the host device and each of the one or more remote devices and allocating access to the buffer of the host device for each of the one or more remote devices responsive to the determined number of dedicated lanes.
摘要翻译：公开了用于分配对主机设备的缓冲器的访问以缓冲在主机设备的控制器和一个或多个远程设备之间传送的数据的方法和装置。主机设备被配置为通过一个或多个相应的专用车道耦合到一个或多个远程设备中的每一个。通过针对与主机设备耦合的一个或多个远程设备中的每一个确定主机设备与一个或多个远程设备中的每一个之间的专用通道的数量来分配缓冲区访问，并且分配对主机设备的缓冲器的访问以供所述一个或多个远程设备中的每一个响应于所确定的专用车道数量。

3. 发明授权

US07506193B1 Systems and methods for overcoming part to part skew in a substrate-mounted circuit 失效
标题翻译：在衬底安装电路中克服部分偏斜的系统和方法
公开(公告)号：US07506193B1
公开(公告)日：2009-03-17
申请号：US11072465
申请日：2005-03-04
申请人： Jason Shoemaker , James P. Balcerek , William E. Oldham , Edward T. Cavanagh, Jr. , Michael J. Bradley
发明人： Jason Shoemaker , James P. Balcerek , William E. Oldham , Edward T. Cavanagh, Jr. , Michael J. Bradley
IPC分类号： G06F1/12
CPC分类号： G06F1/10 , H05K1/0248 , H05K2201/10212
摘要： Variable compensation for part to part skew of components in a substrate-mounted circuit is described. The variability may be provided through a computer software program acting on a programmable delay buffer such that compensation for a skewed signal may be continuously checked against a reference signal or through other methods. The skewed signal may be delayed until the signal matches, within a predetermined margin of error, the reference.
摘要翻译：描述了基板安装电路中部件偏斜的可变补偿。可变性可以通过作用在可编程延迟缓冲器上的计算机软件程序来提供，使得针对参考信号或通过其它方法可以连续检查偏斜信号的补偿。偏移信号可以被延迟，直到信号在预定的误差范围内匹配参考值为止。

4. 发明授权

US5832310A Serial I/O channel having dependent and synchronous sources of control data and user defined data 失效
标题翻译：具有依赖和同步控制数据源和用户定义数据的串行I / O通道
公开(公告)号：US5832310A
公开(公告)日：1998-11-03
申请号：US795457
申请日：1997-02-04
申请人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Gene T. Wieder , Kin H. Ng , William E. Oldham
发明人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Gene T. Wieder , Kin H. Ng , William E. Oldham
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/122
摘要： Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a serial data transfer medium. A data buffer receives and stores user defined data from the parallel storage medium. A control data facility that is distinct from the data buffer forms and transmits control data from the sender of the frame to the recipient of the frame via a path that does not include the data buffer. The control data facility includes respectively different dedicated logic for asynchronously generating each of the following: special character sequences, frame delimiters, headers, and cyclic redundancy checksums. A switching facility receives the user defined data from the data buffer. The switching facility also receives control data from the control data facility. The switching facility provides either the user defined data or the control data to the serial link driver. A data path control mechanism signals the switching facility to alternately provide the control data and the user defined data to the serial link driver, thereby forming frames.
摘要翻译：提供了用于将用户定义的数据从并行存储介质传送到处理器或I / O设备控制器的I / O通道子系统中的串行链路驱动器的装置。串行链路驱动器通过串行数据传输介质发送用户定义的数据帧。数据缓冲器从并行存储介质接收并存储用户定义的数据。与数据缓冲器不同的控制数据设施形成并通过不包括数据缓冲器的路径将控制数据从帧的发送者发送到帧的接收者。控制数据设备分别包括不同的专用逻辑，用于异步地产生以下各项：特殊字符序列，帧分隔符，报头和循环冗余校验和。交换设备从数据缓冲器接收用户定义的数据。交换设备还从控制数据设备接收控制数据。交换设备向用户定义的数据或控制数据提供给串行链路驱动程序。数据路径控制机构发信号通知切换设备，以交替地向串行链路驱动器提供控制数据和用户定义的数据，从而形成帧。

5. 发明授权

US5553302A Serial I/O channel having independent and asynchronous facilities with sequence recognition, frame recognition, and frame receiving mechanism for receiving control and user defined data 失效
标题翻译：串行I / O通道具有独立和异步的设备，具有序列识别，帧识别和用于接收控制和用户定义数据的帧接收机制
公开(公告)号：US5553302A
公开(公告)日：1996-09-03
申请号：US176805
申请日：1993-12-30
申请人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Gene T. Wieder , Kin H. Ng , William E. Oldham
发明人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Gene T. Wieder , Kin H. Ng , William E. Oldham
IPC分类号： G06F13/12 , H04L12/56 , H04L29/08 , G06F13/00
CPC分类号： H04L49/901 , G06F13/128 , H04L49/90 , H04L49/9057 , H04L69/324
摘要： An Input/Output (I/O) subsystem is provided for transferring frames containing frame control data from a serial data transfer medium to a parallel storage medium. The subsystem includes independent components for processing different portions of the received character stream. The subsystem includes a sequence recognition mechanism for receiving and identifying any of a plurality of digital data bit sequences. The sequences represent channel status information from the data transfer medium. The sequence recognition mechanism provides an interrupt signal derived from the sequences. A frame recognition mechanism responds to the interrupt signal. The frame recognition mechanism receives and identifies a start-of-frame delimiter or an end-of-frame delimiter from the data transfer medium. The frame recognition mechanism provides a frame status signal. A frame receiving mechanism responds to the frame status signal. The frame receiving mechanism receives and identifies a frame header from the data transfer medium. The frame receiving mechanism also verifies link and device level I/O protocol compliance asynchronously while any user defined data included in the frame are being received. The frame receiving mechanism also stores the user defined data in the parallel storage medium concurrently with the verification, if any user defined data are included.
摘要翻译：提供输入/输出（I / O）子系统，用于将包含帧控制数据的帧从串行数据传输介质传送到并行存储介质。子系统包括用于处理接收到的字符流的不同部分的独立组件。子系统包括用于接收和识别多个数字数据位序列中的任一个的序列识别机制。这些序列表示来自数据传送介质的信道状态信息。序列识别机制提供从序列导出的中断信号。帧识别机制响应中断信号。帧识别机制从数据传输介质接收并识别帧起始定界符或帧结束定界符。帧识别机制提供帧状态信号。帧接收机制响应帧状态信号。帧接收机构从数据传送介质接收并识别帧头。帧接收机制还在接收到帧中包含的任何用户定义的数据的同时异步地验证链路和设备级I / O协议的合规性。如果包括任何用户定义的数据，帧接收机构也将用户定义的数据与验证同时存储在并行存储介质中。

6. 发明授权

US5463762A I/O subsystem with header and error detection code generation and checking 失效
标题翻译： I / O子系统具有标题和错误检测码生成和检查
公开(公告)号：US5463762A
公开(公告)日：1995-10-31
申请号：US176547
申请日：1993-12-30
申请人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Kin H. Ng
发明人： Douglas E. Morrissey , Edward T. Cavanagh, Jr. , Kin H. Ng
IPC分类号： G06F11/10 , G06F13/38 , G06F1/00
CPC分类号： G06F11/10 , G06F13/385
摘要： Apparatus is provided for use in an Input/Output (I/O) subsystem. The I/O subsystem is coupled to a serial data transfer medium that transmits data from a sender to a recipient. The I/O subsystem processes a frame comprising user defined data and frame control data. The frame is received over the serial data transfer medium. The apparatus includes a mechanism for receiving and validating the frame from the serial data transfer medium. The receiving mechanism transmits the user defined data to a first-in, first-out (FIFO) buffer. A mechanism is provided for forming a block header. The block header comprises control data that are used by the recipient of the user defined data. The block header forming mechanism is distinct from the FIFO buffer. A switching mechanism is coupled to receive the block header and a subset of the user defined data. The recipient has a parallel storage medium. The switching mechanism transmits either the block header or the subset of the user defined data to the parallel storage medium. A control mechanism provides signals to configure the switching mechanism to alternately transmit the block header and the subset of the user defined data to the parallel storage medium. By alternating the block header and data, a data block is formed having a size that equals the native sector size of the recipient.
摘要翻译：设备用于输入/输出（I / O）子系统。 I / O子系统耦合到将数据从发送方传送到接收方的串行数据传输介质。 I / O子系统处理包括用户定义的数据和帧控制数据的帧。帧通过串行数据传输介质接收。该装置包括用于从串行数据传送介质接收和验证帧的机构。接收机制将用户定义的数据发送到先进先出（FIFO）缓冲器。提供了一种用于形成块头的机制。块头包括由用户定义的数据的接收者使用的控制数据。块头形成机制与FIFO缓冲区不同。交换机制被耦合以接收块头部和用户定义的数据的子集。收件人具有并行存储介质。切换机制将块头部或用户定义数据的子集发送到并行存储介质。控制机制提供信号以配置切换机制以将块头部和用户定义数据的子集交替地发送到并行存储介质。通过交替块头和数据，形成具有等于接收者的本机扇区大小的大小的数据块。

7. 发明申请

US20110246686A1 APPARATUS AND SYSTEM HAVING PCI ROOT PORT AND DIRECT MEMORY ACCESS DEVICE FUNCTIONALITY 审中-公开
标题翻译：具有PCI根端口和直接存储器访问设备功能的装置和系统
公开(公告)号：US20110246686A1
公开(公告)日：2011-10-06
申请号：US12752303
申请日：2010-04-01
申请人： Edward T. Cavanagh, JR. , Frederick George Fellenser , John William Bartholomew , Jia Tong
发明人： Edward T. Cavanagh, JR. , Frederick George Fellenser , John William Bartholomew , Jia Tong
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： An apparatus and system having both PCI Root Port (RP) device and Direct Memory Access (DMA) End Point device functionality is disclosed. The apparatus is for use in an input/output (I/O) system interconnect module (IOSIM) device. A DMA/RP module includes a RP portion and one or more DMA/RP portions. The RP portion has one or more queue pipes and is configured to function as a standard PCIe Root Port device. Each of the DMA/RP portions includes DMA engines and DMA input and output channels, and is configured to behave more like an End Point device. The DMA/RP module also includes one or more PCIe hard core portions, an ICAM (I/O Caching Agent Module), and at least one PCIe service block (PSB). *The hard core portion couples the DMA/RP module and IOSIM device to an I/O device via a PCIe link, and the ICAM transitions data to a host memory device operating system.
摘要翻译：公开了具有PCI根端口（RP）设备和直接存储器访问（DMA）端点设备功能）的设备和系统。该设备用于输入/输出（I / O）系统互连模块（IOSIM）设备。 DMA / RP模块包括RP部分和一个或多个DMA / RP部分。 RP部分具有一个或多个队列管道，并且被配置为用作标准PCIe根端口设备。每个DMA / RP部分包括DMA引擎和DMA输入和输出通道，并且被配置为更像终端设备。 DMA / RP模块还包括一个或多个PCIe硬核部分，ICAM（I / O缓存代理模块）和至少一个PCIe服务模块（PSB）。 *硬核部分通过PCIe链路将DMA / RP模块和IOSIM设备耦合到I / O设备，ICAM将数据转换到主机存储设备操作系统。

8. 发明授权

US09026865B2 Software handling of hardware error handling in hypervisor-based systems 有权
标题翻译：基于虚拟机管理程序的系统中的硬件错误处理的软件处理
公开(公告)号：US09026865B2
公开(公告)日：2015-05-05
申请号：US13493023
申请日：2012-06-11
申请人： Mehdi Entezari , Edward T. Cavanagh, Jr. , Bryan E. Thompson
发明人： Mehdi Entezari , Edward T. Cavanagh, Jr. , Bryan E. Thompson
IPC分类号： G06F11/00 , G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45579 , G06F2009/45587
摘要： Errors occurring on a hardware bus of a hypervisor-based system may be handled in software monitors in the hypervisor-based system. When an error occurs, guest partitions on the hypervisor-based system may be notified of the error through a monitor executing in each guest partition. Only guest partitions affected by the error may be shut down or provided other instructions for taking an action in response to the error.
摘要翻译：在基于虚拟机管理程序的系统的硬件总线上发生的错误可以在基于管理程序的系统中的软件监视器中处理。当发生错误时，可以通过在每个客户机分区中执行的监视器通知基于虚拟机管理程序的系统上的客户机分区错误。只有受该错误影响的客户机分区可能会被关闭或提供其他指令来采取行动来应对错误。

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