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1. 发明授权

US4025906A Apparatus for identifying the type of devices coupled to a data processing system controller 失效
标题翻译：用于识别耦合到数据处理系统控制器的设备类型的装置
公开(公告)号：US4025906A
公开(公告)日：1977-05-24
申请号：US643423
申请日：1975-12-22
申请人： Douglas L. Riikonen
发明人： Douglas L. Riikonen
IPC分类号： G06F13/38 , G06F3/04
CPC分类号： G06F13/385 , G05B2219/15028
摘要： Different type devices coupled at random to different channels of a controller therefor, are identified and initial conditions are set by successively comparing known identification codes provided by the controller for known devices with the unknown identification code received from the device whose channel is enabled. In response to positive comparison the identity of the device is known and the controller provides a stored record of such identity and further enables device type specific operations to be provided by the controller.
摘要翻译：识别与其控制器的不同通道耦合的不同类型的设备，并且通过将已知设备的控制器提供的已知识别代码与从其通道启用的设备接收到的未知识别码连续比较来设置初始条件。响应于正比较，设备的身份是已知的，并且控制器提供这种身份的存储记录，并且进一步使控制器提供设备类型特定的操作。

2. 发明授权

US3993981A Apparatus for processing data transfer requests in a data processing system 失效
标题翻译：用于在数据处理系统中处理数据传送请求的装置
公开(公告)号：US3993981A
公开(公告)日：1976-11-23
申请号：US591964
申请日：1975-06-30
申请人： Frank V. Cassarino, Jr. , George J. Barlow , George J. Bekampis , John W. Conway , Richard A. Lemay , David B. O'Keefe , Douglas L. Riikonen , William E. Woods
发明人： Frank V. Cassarino, Jr. , George J. Barlow , George J. Bekampis , John W. Conway , Richard A. Lemay , David B. O'Keefe , Douglas L. Riikonen , William E. Woods
IPC分类号： G06F9/46 , G06F13/18 , G06F13/37 , G06F13/378 , G06F13/42 , G06F3/04 , G06F13/00
CPC分类号： G06F13/378 , G06F13/18 , G06F13/4213
摘要： In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus during asynchronously generated information bus transfer cycles, the units are coupled in a priority network and depending upon their respective priority may gain access to the bus before a lower priority unit is so enabled. Each one of the units includes apparatus for responding to a request for the transfer of information from another unit by providing any one of up to three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for a relatively extended period of time and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.
摘要翻译：在具有多个单元的数据处理系统中，在异步生成的信息总线传送周期期间，通过公共电气总线在其间传送信息而耦合，这些单元耦合在优先网络中，并且根据它们各自的优先级可以访问总线在较低优先级的单元被启用之前。每个单元包括用于通过提供包括表示立即响应的肯定确认信号的多达三个信号响应中的任何一个来响应来自另一个单元的信息传送的请求的装置，指示该单元最多的否定确认信号可能在相对延长的时间段内处于忙碌状态，并且产生准负面响应，指示该单元可能在下一个异步生成的总线传输周期期间准备就绪。

3. 发明授权

US4038537A Apparatus for verifying the integrity of information stored in a data processing system memory 失效
标题翻译：用于验证存储在数据处理系统存储器中的信息的完整性的装置
公开(公告)号：US4038537A
公开(公告)日：1977-07-26
申请号：US643453
申请日：1975-12-22
申请人： Frank V. Cassarino, Jr. , Thomas O. Holtey , Douglas L. Riikonen
发明人： Frank V. Cassarino, Jr. , Thomas O. Holtey , Douglas L. Riikonen
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1008 , G06F11/1076 , G11C29/52
摘要： A memory having a plurality of word locations, each having a bit location, includes a parity word in one of the word locations. Bit selector means selects a column of bits made up of like positioned bits in each of the word locations. All bits in a column are added together to indicate whether there is a successful parity check. Each such column is successively checked thereby verifying the integrity of the stored information on a column basis.

4. 发明授权

US4028668A Apparatus for selectively addressing sections and locations in a device controller's memory 失效
标题翻译：用于选择性地寻址设备控制器（3s存储器）中的部分和位置的装置
公开(公告)号：US4028668A
公开(公告)日：1977-06-07
申请号：US643730
申请日：1975-12-22
申请人： Douglas L. Riikonen
发明人： Douglas L. Riikonen
IPC分类号： G06F12/08 , G06F13/12 , G06F3/04 , G06F13/00
CPC分类号： G06F13/122
摘要： A memory in a device controller divided into sections which are equal in number to the potential number of devices controllable by the controller, each section having a plurality of storage locations for storing the same topology of information in like positioned locations in the other sections is provided, such information including control and status indicators. Apparatus for addressing the locations independent of the addressing of the sections is provided, the sections being addressable independent of the active device or under normal conditions in direct relationship to the identity of the active device so that the information in one section may be changed even though a device associated with another section is then active.
摘要翻译：设备控制器中的存储器被划分为与控制器可控制的设备的潜在数量相等的部分，每个部分具有多个存储位置，用于将相同的拓扑信息存储在其他部分中的类似定位位置中，这些信息包括控制和状态指标。提供了用于寻址独立于部分寻址的位置的装置，这些部分可独立于有效装置寻址，或者在正常条件下与有源装置的身份直接相关，使得即使在一个部分中的信息也可能改变与另一部分相关联的设备然后被激活。

5. 发明授权

US4003033A Architecture for a microprogrammed device controller 失效
标题翻译：微程序设备控制器的架构
公开(公告)号：US4003033A
公开(公告)日：1977-01-11
申请号：US643439
申请日：1975-12-22
申请人： David B. O'Keefe , Frank V. Cassarino, Jr. , Douglas L. Riikonen
发明人： David B. O'Keefe , Frank V. Cassarino, Jr. , Douglas L. Riikonen
IPC分类号： G06F9/22 , G06F9/26 , G06F3/00 , G06F15/16
CPC分类号： G06F9/226 , G06F9/26
摘要： A device controller having a microprogrammed control store for storing instructions useable in the control of the controller and a scratch pad memory for storing device specific information useable in the control and operation of the device is provided. An addressed instruction is received by an instruction register from which control signals are generated. The contents of the instruction register are used to address the control store as well as the scratch pad memory and in addition is received by means of a multiplexor by an arithmetic unit which provides computations in the controller. The multiplexor which in addition receives signals from the scratch pad memory and the devices is also directly coupled to write information in the scratch pad memory. The controller may receive diagnostic and other instructions from a coupled data processor which are then used to control the operation of the controller in place of the instructions in the control store.
摘要翻译：提供了一种具有微程序控制存储器的设备控制器，用于存储可用于控制器的指令和用于存储可用于设备的控制和操作的设备特定信息的便笺本式存储器。寻址指令由生成控制信号的指令寄存器接收。指令寄存器的内容用于对控制存储器以及暂存器存储器进行寻址，并且还通过在控制器中提供计算的算术单元通过多路复用器来接收。另外，从暂存器存储器和器件接收信号的多路复用器也直接耦合到在暂存器存储器中写入信息。控制器可以从耦合的数据处理器接收诊断和其它指令，然后这些指令用于控制控制器的操作来代替控制存储器中的指令。

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