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    • 3. 发明申请
    • METHOD OF DRIVING DISPLAY PANEL AND DISPLAY APPARATUS FOR PERFORMING THE SAME
    • 驱动显示面板的方法和执行其的显示装置
    • US20110187730A1
    • 2011-08-04
    • US12938302
    • 2010-11-02
    • Bong-Ju JUNNam-Gon CHOIJoo-Hwan PARKYong-Bum KIMDong-Hyun YEO
    • Bong-Ju JUNNam-Gon CHOIJoo-Hwan PARKYong-Bum KIMDong-Hyun YEO
    • G09G5/36G09G5/00G09G3/36
    • G09G3/36G09G5/00G09G5/36
    • A display apparatus includes a display panel, a plurality of gate lines driving circuit parts, a plurality of data lines driving circuit parts and a timing control part. The display panel includes a plurality of gate lines and a plurality of data lines. The gate lines driving circuit parts output gate signals to the gate lines. The data lines driving circuit parts output data signals to the data lines. The timing control part applies a dummy gate signal to at least one dummy gate line, controls a latch sequence of image data and an output sequence of the gate lines driving circuit parts in a reverse sequence, in response to an inverted-mounting mode selection signal for displaying an inverted mount image to the display panel. Because signal lines can be shortened, heat generated by the display apparatus may be decreased and image quality of the display apparatus may be improved.
    • 显示装置包括显示面板,多个栅极线驱动电路部分,多个数据线驱动电路部分和定时控制部分。 显示面板包括多条栅极线和多条数据线。 栅极线驱动电路部分将栅极信号输出到栅极线。 数据线驱动电路部分向数据线输出数据信号。 定时控制部分对至少一个虚拟栅极线施加虚拟栅极信号,响应于反向安装模式选择信号,以相反的顺序控制图像数据的锁存序列和栅极线驱动电路部分的输出序列 用于向显示面板显示反转安装图像。 由于可以缩短信号线,所以显示装置产生的热量可能会降低,从而可以提高显示装置的图像质量。
    • 4. 发明申请
    • DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME
    • 显示装置及其驱动方法
    • US20100309182A1
    • 2010-12-09
    • US12788505
    • 2010-05-27
    • Yong-Bum KIMByung-Kil JEONDong-Hyun YEO
    • Yong-Bum KIMByung-Kil JEONDong-Hyun YEO
    • G09G5/00
    • G09G3/3611G09G2310/027G09G2330/06G09G2370/08
    • A display apparatus includes a display part, a signal control part, data driving parts, and first and second wiring pairs. The display part includes pixels. The signal control part includes a transmission part that converts an image signal into a multi-level signal. The data driving parts receive the multi-level signal from the transmission part, convert the multi-level signal into a reproduced image signal and provide the pixels with the reproduced image signal. The first and second wiring pairs connect the transmission part and at least one data driving part of the data driving parts. The multi-level signal includes serial data of the image signal and an embedding clock embedded in the serial data. A voltage level of the serial data in the multi-level signal is different from a voltage level of the embedding clock in the multi-level signal.
    • 显示装置包括显示部分,信号控制部分,数据驱动部分以及第一和第二布线对。 显示部分包括像素。 信号控制部分包括将图像信号转换为多电平信号的传输部分。 数据驱动部分从发送部分接收多电平信号,将多电平信号转换为再现图像信号,并为像素提供再现的图像信号。 第一和第二布线将传输部分和数据驱动部分的至少一个数据驱动部分连接起来。 多电平信号包括图像信号的串行数据和嵌入在串行数据中的嵌入时钟。 多电平信号中的串行数据的电压电平与多电平信号中的嵌入时钟的电压电平不同。
    • 8. 发明申请
    • USING MEMORIES TO CHANGE DATA PHASE OR FREQUENCY
    • 使用记忆来更改数据相位或频率
    • US20090125750A1
    • 2009-05-14
    • US12116762
    • 2008-05-07
    • Jae-hyoung ParkWoo-chul KimIk-hyun AhnNam-gon ChoiDong-hyun YeoYoung-su Han
    • Jae-hyoung ParkWoo-chul KimIk-hyun AhnNam-gon ChoiDong-hyun YeoYoung-su Han
    • G06F13/00G06F12/00G06F1/12G06F3/00
    • G06F13/4243
    • A data processing apparatus includes a first memory which comprises a first input/output port and a second input/output port; a second memory which is connected to the first memory and comprises a third input/output port; and a controller for controlling the first and second memories to perform operations of: (a) writing data to the first memory through the first input/output port; (b) reading the data from the first memory through the second input/output port; (c) writing the data read out of the first memory to the second memory through the third input/output port; and (d) reading the data from the second memory through the third input/output port; wherein the operation (a) is performed at a first frequency and the operations (b), (c), (d) are each performed at a second frequency, wherein either: (i) the first frequency is different from the second frequency, or (ii) the first frequency is equal to the second frequency but in each of the operations (b), (c) and (d) the data is different in phase than in the operation (a).
    • 数据处理装置包括:第一存储器,包括第一输入/输出端口和第二输入/输出端口; 第二存储器,其连接到第一存储器并且包括第三输入/输出端口; 以及控制器,用于控制第一和第二存储器以执行以下操作:(a)通过第一输入/输出端口将数据写入第一存储器; (b)通过第二输入/输出端口读取来自第一存储器的数据; (c)通过第三输入/输出端口将从第一存储器读出的数据写入第二存储器; 和(d)通过第三输入/输出端口读取来自第二存储器的数据; 其中所述操作(a)以第一频率执行,并且操作(b),(c),(d)分别以第二频率执行,其中:(i)所述第一频率不同于所述第二频率, 或者(ii)第一频率等于第二频率,但是在每个操作(b),(c)和(d)中,数据的相位与操作(a)不同。
    • 10. 发明授权
    • Timing controller, display apparatus including the same, and method of driving the same
    • 定时控制器,包括其的显示装置及其驱动方法
    • US08933917B2
    • 2015-01-13
    • US13182782
    • 2011-07-14
    • Yong-Bum KimBong-Ju JunDong-Hyun YeoSang Keun Lee
    • Yong-Bum KimBong-Ju JunDong-Hyun YeoSang Keun Lee
    • G06F3/038G09G3/20G09G3/36G09G5/00
    • G09G3/2096G09G3/3648G09G5/008G09G2330/06
    • A timing controller includes a receiver, an internal clock generator, a first frequency converter, a first selector and a control signal generator. The receiver receives an image signal and a main clock signal having a first spread spectrum frequency from an external system, converts the main clock signal to a converted main clock signal and the image signal to a first converted image signal, and outputs the converted main clock signal as a first clock signal having a plurality of frequencies. The internal clock generator multiplies the frequencies of the first clock signal and generates a second clock signal having a frequency band within the multiplied frequencies of the first clock signal. The first frequency converter converts the second clock signal to a third clock signal having a second spread spectrum frequency. The first selector selects one of the second clock signal and the third clock signal in response to a first selection signal and outputs the selected one of the second clock signal and the third clock signal as a control clock signal. The control signal generator receives the control clock signal to generate a control signal synchronized with the control clock signal.
    • 定时控制器包括接收器,内部时钟发生器,第一变频器,第一选择器和控制信号发生器。 接收机从外部系统接收具有第一扩频频率的图像信号和主时钟信号,将主时钟信号转换为转换后的主时钟信号,将图像信号转换为第一转换图像信号,并输出转换后的主时钟 信号作为具有多个频率的第一时钟信号。 内部时钟发生器乘以第一时钟信号的频率,并产生具有在第一时钟信号的相乘频率内的频带的第二时钟信号。 第一变频器将第二时钟信号转换成具有第二扩频频率的第三时钟信号。 第一选择器响应于第一选择信号选择第二时钟信号和第三时钟信号之一,并将所选择的第二时钟信号和第三时钟信号中的一个作为控制时钟信号输出。 控制信号发生器接收控制时钟信号以产生与控制时钟信号同步的控制信号。