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1. 发明授权

US08788744B2 Memory control device 有权
标题翻译：内存控制装置
公开(公告)号：US08788744B2
公开(公告)日：2014-07-22
申请号：US13453169
申请日：2012-04-23
申请人： Shuang-Yi Tan , Yueh-Yao Nain , Der-Ing Hsu
发明人： Shuang-Yi Tan , Yueh-Yao Nain , Der-Ing Hsu
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0238 , G06F13/1684 , G06F13/4022
摘要： A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal.
摘要翻译：提供了一种用于控制主控制器和辅助控制器以访问闪速存储器的存储器控制装置。总线开关分别通过第一，第二和第三串行外设接口（SPI）总线耦合到主控制器，次控制器和闪存。选择单元将第三SPI总线选择性地耦合到第一和第二总线之一。当总线交换机通过第一SPI总线接收到来自主控制器的访问请求时，选择单元将第三SPI总线耦合到第一SPI总线，以便传输芯片选择信号，时钟信号和主输出从机输入（MOSI）信号从主控制器到闪存，用于访问闪存。第一访问请求由第一片选信号提供。

2. 发明申请

US20130097363A1 MEMORY CONTROL DEVICE 有权
标题翻译：存储控制装置
公开(公告)号：US20130097363A1
公开(公告)日：2013-04-18
申请号：US13453169
申请日：2012-04-23
申请人： SHUANG-YI TAN , Yueh-Yao Nain , Der-Ing Hsu
发明人： SHUANG-YI TAN , Yueh-Yao Nain , Der-Ing Hsu
IPC分类号： G06F12/00
CPC分类号： G06F12/0238 , G06F13/1684 , G06F13/4022
摘要： A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal.
摘要翻译：提供了一种用于控制主控制器和辅助控制器以访问闪速存储器的存储器控制装置。总线开关分别通过第一，第二和第三串行外设接口（SPI）总线耦合到主控制器，次控制器和闪存。选择单元将第三SPI总线选择性地耦合到第一和第二总线之一。当总线交换机通过第一SPI总线接收到来自主控制器的访问请求时，选择单元将第三SPI总线耦合到第一SPI总线，以便传输芯片选择信号，时钟信号和主输出从机输入（MOSI）信号从主控制器到闪存，用于访问闪存。第一访问请求由第一片选信号提供。

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