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1. 发明授权

US07630741B2 Compact and durable messenger device 失效
标题翻译：紧凑耐用的信使装置
公开(公告)号：US07630741B2
公开(公告)日：2009-12-08
申请号：US11318377
申请日：2005-12-23
申请人： Kabir Siddiqui , David W. Voth
发明人： Kabir Siddiqui , David W. Voth
IPC分类号： H04M1/00
CPC分类号： G06F1/1683 , G06F1/1616 , G06F1/1626 , G06F1/1647 , G06F1/1658 , G06F1/1662 , G06F1/1671 , G06F1/1681
摘要： The subject innovation and/or methods relate to a compact durable communication device that can include a plurality of improvements to provide durability and thinness. The devices can be a clamshell smartphone, a messenger device, a thin smartphone, and/or any other suitable mobile communication device. The improvements can include a magnesium plate, an opening for an electrical component associated with the plate, internal antenna placement, an extended backlight for a dual display, and/or a mono hinge to provide connectivity.
摘要翻译：主题创新和/或方法涉及紧凑的耐用通信设备，其可以包括多个改进以提供耐久性和薄度。这些设备可以是蛤壳式智能电话，信使设备，薄智能电话和/或任何其它合适的移动通信设备。改进可以包括镁板，用于与板相关联的电气部件的开口，内部天线放置，双显示器的延伸背光和/或提供连接的单声道铰链。

2. 发明授权

US5787246A System for configuring devices for a computer system 失效
标题翻译：用于为计算机系统配置设备的系统
公开(公告)号：US5787246A
公开(公告)日：1998-07-28
申请号：US250698
申请日：1994-05-27
申请人： Moshe Lichtman , Mark R. Enstrom , Thomas E. Lennon , Ralph A. Lipe , Pierre-Yves Santerre , Robert T. Short , David W. Voth
发明人： Moshe Lichtman , Mark R. Enstrom , Thomas E. Lennon , Ralph A. Lipe , Pierre-Yves Santerre , Robert T. Short , David W. Voth
IPC分类号： G06F9/445 , G06F15/177 , G06F15/02 , G06F12/02 , G06F15/40
CPC分类号： G06F9/4411 , G06F15/177
摘要： A system for configuring devices of a computer system without user intervention. Device information for each of the devices is collected to uniquely identify the devices and to describe the device characteristics associated with the operation of devices with the computer. Computer resources, which support the functions of the devices within the computer, are allocated based upon the device information. This allocation process prevents a potential conflicting use of the resources by the devices. A device driver, which enables communications between the corresponding device and the computer system, is also identified for each of the devices in response to the device information. In response to the allocation of resources, the identified device drivers are loaded and the devices are activated for operation with the computer.
摘要翻译：用于配置计算机系统的设备而无需用户干预的系统。收集每个设备的设备信息以唯一地识别设备并且描述与具有计算机的设备的操作相关联的设备特性。基于设备信息分配支持计算机内的设备的功能的计算机资源。此分配过程可防止设备潜在地冲突使用资源。响应于设备信息，还针对每个设备识别用于实现相应设备和计算机系统之间的通信的设备驱动程序。响应于资源的分配，识别的设备驱动程序被加载并且设备被激活以与计算机一起操作。

3. 发明授权

US5768542A Method and apparatus for automatically configuring circuit cards in a computer system 失效
公开(公告)号：US5768542A
公开(公告)日：1998-06-16
申请号：US774998
申请日：1996-12-27
申请人： Mark R. Enstrom , Ralph L. Lipe , David W. Voth , Robert T. Short , Narendar B. Sahgal , Ajay V. Bhatt , Philip W. Martin , Sudarshan Bala Cadambi
发明人： Mark R. Enstrom , Ralph L. Lipe , David W. Voth , Robert T. Short , Narendar B. Sahgal , Ajay V. Bhatt , Philip W. Martin , Sudarshan Bala Cadambi
IPC分类号： G06F13/40 , G06F13/12 , G06F13/14
CPC分类号： G06F13/4072
摘要： A method and apparatus for automatically configuring circuit cards used in a computer system. The present invention includes a method and apparatus that enables the circuit cards to be automatically configured during system boot up without any user intervention. The present invention also includes a method for the computer system software to detect resources requested by the circuit cards in order to resolve any system resource conflicts.

4. 发明授权

US5537415A Multi-channel personal messaging unit 失效
标题翻译：多通道个人信息单元
公开(公告)号：US5537415A
公开(公告)日：1996-07-16
申请号：US336268
申请日：1994-11-08
申请人： J. Mark Miller , David W. Voth
发明人： J. Mark Miller , David W. Voth
IPC分类号： H04W88/06 , H04Q7/14 , H04J3/16
CPC分类号： H04W88/06
摘要： A mobile communications system in accordance with the invention comprises primary and secondary wireless digital communications networks. The system also comprises a wireless mobile messaging unit. The primary wireless digital communications network operates on a first communications channel using a reserved time slot protocol having discrete time slots reserved for data transmissions to the mobile messaging unit. The secondary wireless digital communications network operates on a second communications channel using a continuous downlink protocol under which data transmissions to the mobile messaging unit might take place at any time. The wireless mobile messaging unit has channel selection logic operatively connected to tune the mobile messaging unit to the first communications channel during the discrete time slots and to the second communications channel during other times. This allows the mobile unit to communicate concurrently with both of the primary and secondary digital communication networks, while requiring only a single radio receiver or transceiver.
摘要翻译：根据本发明的移动通信系统包括主要和次要无线数字通信网络。该系统还包括无线移动消息单元。主要无线数字通信网络使用保留的时隙协议在第一通信信道上操作，所述预留时隙协议具有保留用于向移动消息收发单元进行数据传输的离散时隙。辅助无线数字通信网络使用连续下行链路协议在第二通信信道上操作，在该下行链路协议下，可以在任何时间发生对移动消息接发单元的数据传输。无线移动消息接收单元具有可操作地连接的信道选择逻辑，以便在离散时隙期间将移动消息收发单元调谐到第一通信信道，而在其他时间期间调谐到第二通信信道。这允许移动单元与主要和次要数字通信网络同时通信，同时仅需要一个无线电接收器或收发器。

5. 发明授权

US08174508B2 Pointing and data entry input device 有权
标题翻译：指向和数据输入输入设备
公开(公告)号：US08174508B2
公开(公告)日：2012-05-08
申请号：US11941985
申请日：2007-11-19
申请人： Michael J. Sinclair , Ray A. Bittner , David W. Voth
发明人： Michael J. Sinclair , Ray A. Bittner , David W. Voth
IPC分类号： G06F3/045
CPC分类号： G06F3/0202 , G06F3/044 , G06F3/04886 , H01H2003/0293 , H01H2217/01 , H01H2217/036 , H01H2239/006 , H03K2217/96054 , H04M1/23
摘要： An input device includes an array of adjacent capacitive sensors arranged into rows and columns. Each capacitive sensor exhibits a capacitance characteristic when in proximity to a conductive element. A plurality of mechanical hysteresis mechanisms are each deposited on and in contact with each of the capacitive sensors and configured to be actuated by a corresponding push button. Each capacitive sensor exhibits an electrical characteristic upon actuation of the corresponding mechanical hysteresis mechanism. An insulating overlay layer positioned over the array of capacitive sensors and the plurality of mechanical hysteresis mechanisms defines each push button and defines a surface for accommodating the conductive element.
摘要翻译：输入装置包括布置成行和列的相邻电容传感器阵列。每个电容传感器在接近导电元件时表现出电容特性。多个机械滞后机构各自沉积在每个电容传感器上并与之接触，并且被配置为由相应的按钮致动。每个电容传感器在相应的机械滞后机构的致动时表现出电特性。位于电容传感器阵列上方的绝缘覆盖层和多个机械滞后机构限定每个按钮并且限定用于容纳导电元件的表面。

6. 发明申请

US20090128511A1 POINTING AND DATA ENTRY INPUT DEVICE 有权
标题翻译：指针和数据输入设备
公开(公告)号：US20090128511A1
公开(公告)日：2009-05-21
申请号：US11941985
申请日：2007-11-19
申请人： Michael J. Sinclair , Ray A. Bittner, JR. , David W. Voth
发明人： Michael J. Sinclair , Ray A. Bittner, JR. , David W. Voth
IPC分类号： G06F3/045
CPC分类号： G06F3/0202 , G06F3/044 , G06F3/04886 , H01H2003/0293 , H01H2217/01 , H01H2217/036 , H01H2239/006 , H03K2217/96054 , H04M1/23
摘要： An input device includes an array of adjacent capacitive sensors arranged into rows and columns. Each capacitive sensor exhibits a capacitance characteristic when in proximity to a conductive element. A plurality of mechanical hysteresis mechanisms are each deposited on and in contact with each of the capacitive sensors and configured to be actuated by a corresponding push button. Each capacitive sensor exhibits an electrical characteristic upon actuation of the corresponding mechanical hysteresis mechanism. An insulating overlay layer positioned over the array of capacitive sensors and the plurality of mechanical hysteresis mechanisms defines each push button and defines a surface for accommodating the conductive element.
摘要翻译：输入装置包括布置成行和列的相邻电容传感器阵列。每个电容传感器在接近导电元件时表现出电容特性。多个机械滞后机构各自沉积在每个电容传感器上并与之接触，并且被配置为由相应的按钮致动。每个电容传感器在相应的机械滞后机构的致动时表现出电特性。位于电容传感器阵列上方的绝缘覆盖层和多个机械滞后机构限定每个按钮并且限定用于容纳导电元件的表面。

7. 发明授权

US5638028A Circuit for generating a low power CPU clock signal 失效
标题翻译：用于产生低功耗CPU时钟信号的电路
公开(公告)号：US5638028A
公开(公告)日：1997-06-10
申请号：US541207
申请日：1995-10-12
申请人： David W. Voth
发明人： David W. Voth
IPC分类号： H03L7/08 , H03L7/099 , H03L7/18 , H03L7/181 , H03L7/06
CPC分类号： H03L7/0997 , H03L7/0802 , H03L7/0992 , H03L7/181 , H03L7/18
摘要： A circuit for generating a low power CPU clock signal is disclosed. The circuit includes a multi-frequency oscillator having a plurality of output signals of various frequencies that are input to a signal selector. The signal selector is controlled to route one of the various frequency signals to the output, which provides the CPU clock oscillating signal. The frequency of the CPU clock signal is compared against a reference oscillatory signal that is generated by a reference oscillator. Based upon the comparison, the frequency comparator generates an output signal that is used to control the signal selector to select an input signal of either higher or lower frequency, depending upon the comparison. Finally, an enable signal is provided for selectively enabling the operation of the CPU clock oscillating circuit.
摘要翻译：公开了一种用于产生低功率CPU时钟信号的电路。该电路包括具有输入到信号选择器的各种频率的多个输出信号的多频振荡器。控制信号选择器将各种频率信号中的一个传送到输出，从而提供CPU时钟振荡信号。将CPU时钟信号的频率与由参考振荡器产生的参考振荡信号进行比较。基于比较，频率比较器根据比较器产生用于控制信号选择器选择较高或较低频率的输入信号的输出信号。最后，提供使能信号，用于选择性地启用CPU时钟振荡电路的操作。

8. 发明授权

US5581669A System and method for peripheral data transfer 失效
标题翻译：用于外围数据传输的系统和方法
公开(公告)号：US5581669A
公开(公告)日：1996-12-03
申请号：US161785
申请日：1993-12-03
申请人： David W. Voth
发明人： David W. Voth
IPC分类号： G06F3/12 , G06F13/00 , G06F13/38 , G06F13/42 , G06F15/00
CPC分类号： G06F13/385 , G06F13/4226 , G06F2213/0004
摘要： A system and method for increasing the rate of data transfer from a host computer to a peripheral such as a printer without the need for special hardware within the host computer or a special interface cable coupling the host computer to the peripheral. Data is transferred from the host computer to the peripheral in 4 Kbyte bursts. Handshaking occurs between the host computer and the peripheral only between bursts. Bytes of peripheral data are apportioned into multiple bytes of data within the host computer. The multiple bytes are transmitted from the host computer to the peripheral, each transmitted byte containing a data clock and several bits of peripheral data. In one embodiment, the peripheral data byte is apportioned into two bytes within the host computer with each byte having a pair of clock signals transmitted along with the peripheral data portion. In another embodiment, three bytes of peripheral data are apportioned into four bytes within the host computer with each byte having a single clock signal transmitted along with the peripheral data portion. Within the peripheral, a clock circuit detects the clock signal from each transmitted byte and generates a delayed signal to latch peripheral data bytes into a storage register. In addition, the first transmitted byte contains a flag to signal the peripheral that the data that follows is RLE compressed data. Parity bits are also included in the transmitted data. The system can be easily implemented on any Centronics compatible printer system to increase the rate of data transfer.
摘要翻译：一种用于增加从主计算机到诸如打印机的外围设备的数据传输速率的系统和方法，而不需要在主计算机内的特殊硬件或者将主计算机耦合到外围设备的特殊接口电缆。数据从主计算机传输到外围设备，以4 KB的脉冲串。只有在突发之间，主机和外围设备之间才会发生握手。外设数据的字节数在主计算机内分配为多个字节的数据。多个字节从主机传输到外围设备，每个发送的字节包含一个数据时钟和几个外围数据位。在一个实施例中，外围数据字节在主计算机内分配成两个字节，每个字节具有与外围数据部分一起发送的一对时钟信号。在另一个实施例中，三个字节的外围数据在主计算机内分配成四个字节，每个字节具有与外围数据部分一起发送的单个时钟信号。在外围设备中，时钟电路从每个发送的字节检测时钟信号，并产生延迟的信号，将外围数据字节锁存到存储寄存器中。另外，第一个发送的字节包含用于向外围设备发信号的标志，下面的数据是RLE压缩数据。发送数据中也包含奇偶校验位。该系统可以轻松地在任何Centronics兼容的打印机系统上实现，以提高数据传输速率。

9. 发明授权

US06526465B1 PCI and compactpci integration 有权
标题翻译： PCI和compactpci集成
公开(公告)号：US06526465B1
公开(公告)日：2003-02-25
申请号：US09324635
申请日：1999-06-02
申请人： David W. Voth , Ray A. Bittner, Jr.
发明人： David W. Voth , Ray A. Bittner, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/409 , H05K1/18
摘要： A computer system includes a centerplane formed by a printed circuit board. The centerplane has a plurality of Desktop PCI electrical connectors on one side and a plurality of CompactPCI electrical connectors on the other. This allows the use of both Desktop and CompactPCI boards in a signal bus board, without requiring complex bridging circuits. In addition, this allows additional boards to be used without extending the length of the PCI bus.
摘要翻译：计算机系统包括由印刷电路板形成的中心面。中心面在一侧具有多个Desktop PCI电连接器，另一侧具有多个CompactPCI电连接器。这允许在信号总线板中使用Desktop和CompactPCI板，而不需要复杂的桥接电路。此外，这允许在不延长PCI总线长度的情况下使用额外的电路板。

10. 发明授权

US6058263A Interface hardware design using internal and external interfaces 失效
标题翻译：接口硬件设计采用内部和外部接口
公开(公告)号：US6058263A
公开(公告)日：2000-05-02
申请号：US659084
申请日：1996-06-03
申请人： David W. Voth
发明人： David W. Voth
IPC分类号： G06F15/78 , G06F17/50 , G06F13/00
CPC分类号： G06F17/5027 , G06F15/7867 , G06F17/5045
摘要： A computer system includes a plurality of discrete computer components and an integrated circuit that interfaces between the discrete computer components. The integrated circuit has internal hardware interfaces corresponding to respective discrete computer components. The internal hardware interfaces are selected from a limited number of available pre-defined internal hardware interfaces for general kinds of computer components. The internal hardware interfaces are accessible only within the integrated circuit. The integrated circuit further includes component-specific hardware interfaces for connecting the individual discrete components to the selected pre-defined internal HDL interfaces. The component-specific hardware interfaces are designed individually for the different discrete computer components to interface the discrete components to the internal hardware interfaces. A development system is disclosed for use during development of such a computer system. The development system includes interconnections that allow functions to be easily moved from the integrated circuit to a system CPU.
摘要翻译：计算机系统包括多个离散计算机部件和在分立计算机部件之间进行接口的集成电路。集成电路具有对应于相应的分立计算机组件的内部硬件接口。内部硬件接口从有限数量的可用的预定义内部硬件接口中选择，用于一般种类的计算机组件。内部硬件接口只能在集成电路内部访问。集成电路还包括用于将各个分立组件连接到所选择的预定义内部HDL接口的组件专用硬件接口。特定于组件的硬件接口是针对不同的离散计算机组件单独设计的，以将分立组件与内部硬件接口相连接。公开了一种在这种计算机系统的开发期间使用的开发系统。开发系统包括允许功能从集成电路容易地移动到系统CPU的互连。

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