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1. 发明授权

US09043526B2 Versatile lane configuration using a PCIe PIe-8 interface 有权
标题翻译：使用PCIe PIe-8接口的通用通道配置
公开(公告)号：US09043526B2
公开(公告)日：2015-05-26
申请号：US13528146
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F13/40
CPC分类号： G06F13/4018 , G06F9/4411 , G06F13/423
摘要： Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.
摘要翻译：每个PCIe设备可以包括支持多个不同通道配置的媒体访问控制（MAC）接口和物理（PHY）接口。这些接口可以包括支持1×32,2×16,4×8,8×4,16×2和32×1通信的硬件模块。代替使用专用迹线将MAC接口中的每个硬件模块物理连接到PHY接口中的相应硬件模块，该设备可以包括两个总线控制器，其仲裁哪些硬件模块连接到耦合两个接口的内部总线。当需要不同的通道配置时，总线控制器将相应的硬件模块耦合到内部总线。以这种方式，不同的通道配置与其他通道配置共享总线的相同通道（和线）。因此，共享总线仅需要包括足够的通道（和电线），以适应最宽的通道配置。

2. 发明申请

US20130346665A1 VERSATILE LANE CONFIGURATION USING A PCIE PIE-8 INTERFACE 有权
公开(公告)号：US20130346665A1
公开(公告)日：2013-12-26
申请号：US13528146
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F13/20
CPC分类号： G06F13/4018 , G06F9/4411 , G06F13/423
摘要： Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

3. 发明申请

US20120311221A1 USING A PCI STANDARD HOT PLUG CONTROLLER TO MODIFY THE HIERARCHY OF A DISTRIBUTED SWITCH 有权
标题翻译：使用PCI标准热插拔控制器来修改分布式开关的分层
公开(公告)号：US20120311221A1
公开(公告)日：2012-12-06
申请号：US13528192
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F13/20
CPC分类号： G06F13/4081 , G06F13/20
摘要： The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.
摘要翻译：标准热插拔控制器（SHPC）规范可用于在分布式交换机中生成PCI消息，以断开和/或连接端点的虚拟层次与基于多根输入/输出虚拟化（MR-IOV）连接的主机）。管理控制器可以指示SHPC生成指定特定虚拟层级以与特定主机断开连接的PCI分组。连接到主机和SHPC的上行端口接收PCI分组，并使用标识分组中的虚拟端点的报头来索引到路由表中，以识别连接到端点的分布式交换机中的下游端口。一旦PCI数据包穿过交换机并到达下游端口，下游端口会更改路由逻辑，逻辑上将主机与指定的虚拟层次结构断开连接。

4. 发明授权

US08949499B2 Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch 有权
公开(公告)号：US08949499B2
公开(公告)日：2015-02-03
申请号：US13528192
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： H05K7/10 , G06F13/40 , G06F13/20
CPC分类号： G06F13/4081 , G06F13/20
摘要： The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.

5. 发明授权

US08706938B2 Bandwidth limiting on generated PCIE packets from debug source 失效
标题翻译：从调试源生成的PCIE数据包的带宽限制
公开(公告)号：US08706938B2
公开(公告)日：2014-04-22
申请号：US13528224
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F11/263 , G06F13/00 , G06F13/1605 , G06F13/36 , G06F2213/0026
摘要： Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.
摘要翻译：用于执行用于调节带宽的操作的方法，电路和系统，所述操作包括在存储器处接收调试数据分组和用于在共享总线上传送的功能数据分组。然后，该操作通过共享总线将功能数据分组和一个或多个调试数据分组根据调制数据分组的预定比率发送到功能数据分组。然后，该操作将接收到的调试数据分组中的一个或多个丢弃在存储器处，并维持一个或多个丢弃的调试数据分组的计数。然后，操作基于计数更新预定义的比例，并且使用更新的预定义比率来发送功能数据分组和一个或多个调试数据分组。

6. 发明申请

US20130346801A1 BANDWIDTH LIMITING ON GENERATED PCIE PACKETS FROM DEBUG SOURCE 失效
标题翻译：来自调试源的生成PCIE分组的带宽限制
公开(公告)号：US20130346801A1
公开(公告)日：2013-12-26
申请号：US13528224
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F11/28
CPC分类号： G06F11/263 , G06F13/00 , G06F13/1605 , G06F13/36 , G06F2213/0026
摘要： Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.
摘要翻译：用于执行用于调节带宽的操作的方法，电路和系统，所述操作包括在存储器处接收调试数据分组和用于在共享总线上传送的功能数据分组。然后，该操作通过共享总线将功能数据分组和一个或多个调试数据分组根据调制数据分组的预定比率发送到功能数据分组。然后，该操作将接收到的调试数据分组中的一个或多个丢弃在存储器处，并维持一个或多个丢弃的调试数据分组的计数。然后，操作基于计数更新预定义的比例，并且使用更新的预定义比率来发送功能数据分组和一个或多个调试数据分组。

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