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1. 发明公开

EP2769253A1 MOLDED GLASS LID FOR WAFER LEVEL PACKAGING OF OPTO-ELECTRONIC ASSEMBLIES 有权转让
标题翻译： PRESS玻璃盖板进行封装晶片级光电安排
公开(公告)号：EP2769253A1
公开(公告)日：2014-08-27
申请号：EP12784181.5
申请日：2012-10-19
申请人： Cisco Technology, Inc. , Desai, Kishor , Kachru, Ravinder , Patel, Vipulkumar , Dama, Bipin , Shastri, Kalpendu , Pathak, Soham
发明人： DESAI, Kishor , KACHRU, Ravinder , PATEL, Vipulkumar , DAMA, Bipin , SHASTRI, Kalpendu , PATHAK, Soham
IPC分类号： G02B6/42 , H01L25/16
摘要： An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

2. 发明申请

WO2012141828A2 OPTICAL MODULATOR UTILIZING UNARY ENCODING AND AUXILIARY MODULATOR SECTION FOR LOAD BALANCING 审中-公开
标题翻译：用于负载平衡的光学调制器用于编码和辅助调制器部分
公开(公告)号：WO2012141828A2
公开(公告)日：2012-10-18
申请号：PCT/US2012028159
申请日：2012-03-08
申请人： LIGHTWIRE LLC , METZ PETER C , DAMA BIPIN , SHASTRI KALPENDU
发明人： METZ PETER C , DAMA BIPIN , SHASTRI KALPENDU
CPC分类号： G02F1/011 , G02F1/225 , G02F2001/0113 , H04B10/5051 , H04B10/5053 , H04B10/516
摘要： An optical modulator is configured to include multiple modulating sections formed along each arm and create a unary-encoded optical output signal by driving the number of sections required to represent the data value being transmitted (e.g., three sections driven to represent the data value "3", four sections driven to represent the data value "4"). An auxiliary modulating section, isolated from the optical signal path, is included for creating a path for current flow in situations where only an odd number of modulating sections are required to represent the data. The activation of the auxiliary modulation section minimizes the current imbalance that would otherwise be present along a common node of the arrangement.
摘要翻译：光调制器被配置为包括沿着每个臂形成的多个调制部分，并且通过驱动表示所传送的数据值所需的部分数量（例如，驱动以表示数据值“3”的三个部分）来创建一次编码的光输出信号 “，四个部分被驱动以表示数据值”4“）。包括与光信号路径隔离的辅助调制部分，用于在只需要奇数个调制部分来表示数据的情况下创建用于电流的路径。辅助调制部分的激活使得沿着该装置的公共节点将存在的电流不平衡最小化。

3. 发明申请

WO2008051429A3 OPTICAL MODULATOR UTILIZING MULTI-LEVEL SIGNALING 审中-公开
标题翻译：光调制器利用多级信号
公开(公告)号：WO2008051429A3
公开(公告)日：2008-08-21
申请号：PCT/US2007022200
申请日：2007-10-18
申请人： SIOPTICAL INC , SHASTRI KALPENDU , DAMA BIPIN
发明人： SHASTRI KALPENDU , DAMA BIPIN
IPC分类号： G02F1/035
CPC分类号： G02F1/2255 , G02F1/0123 , H04B10/541
摘要： An optical modulator is formed to include a plurality of separate electrodes disposed along one arm, the electrodes having different lengths and driven with different signals to provide for multi-level signaling (e.g., PAM-4 signaling). By using separate drivers to energize the different sections, the number of sections energized at a given point in time will define the net phase shift introduced to the optical signal. The total length of the combined modulator sections is associated with a p phase shift (180°). Each section is driven by either a digital "one" or "zero", so as to create the multi-level modulation. An essentially equal change in power between adjacent transmitted symbols is accomplished by properly adjusting the lengths of each individual section.
摘要翻译：光学调制器被形成为包括沿着一个臂设置的多个单独的电极，这些电极具有不同的长度并且以不同的信号驱动以提供多级信令（例如，PAM-4信令）。通过使用单独的驱动器来激励不同的部分，在给定时间点激励的部分的数量将限定引入光信号的净相移。组合调制器部分的总长度与p相移（180°）相关联。每个部分由数字“一”或“零”驱动，以创建多级调制。通过适当调整每个单独部分的长度来实现相邻发射符号之间的功率的基本相等的变化。

4. 发明申请

WO2008051429A2 OPTICAL MODULATOR UTILIZING MULTI-LEVEL SIGNALING 审中-公开
标题翻译：光学调制器利用多级信号
公开(公告)号：WO2008051429A2
公开(公告)日：2008-05-02
申请号：PCT/US2007/022200
申请日：2007-10-18
申请人： SIOPTICAL, INC. , SHASTRI, Kalpendu , DAMA, Bipin
发明人： SHASTRI, Kalpendu , DAMA, Bipin
IPC分类号： G02F1/035
CPC分类号： G02F1/2255 , G02F1/0123 , H04B10/541
摘要： An optical modulator is formed to include a plurality of separate electrodes disposed along one arm, the electrodes having different lengths and driven with different signals to provide for multi-level signaling (e.g., PAM-4 signaling). By using separate drivers to energize the different sections, the number of sections energized at a given point in time will define the net phase shift introduced to the optical signal. The total length of the combined modulator sections is associated with a π phase shift (180°). Each section is driven by either a digital "one" or "zero", so as to create the multi-level modulation. An essentially equal change in power between adjacent transmitted symbols is accomplished by properly adjusting the lengths of each individual section.
摘要翻译：光学调制器被形成为包括沿着一个臂布置的多个单独的电极，电极具有不同的长度并用不同的信号驱动以提供多级信号（例如，PAM-4信令）。通过使用单独的驱动器来激励不同的部分，在给定时间点通电的部分的数量将定义引入光信号的净相移。组合调制器部分的总长度与p相移（180°）相关。每个部分由数字“一”或“零”驱动，以创建多级调制。通过适当调整每个单独部分的长度来实现相邻传输符号之间的功率基本上相等的变化。

5. 发明申请

WO2006116747A2 COMMON ELECTRONIC DISPERSION COMPENSATION ARRANGEMENT FOR USE WITH MULTIPLE OPTICAL COMMUNICATION CHANNELS 审中-公开
标题翻译：用于多光通信通道的通用电子分散补偿装置
公开(公告)号：WO2006116747A2
公开(公告)日：2006-11-02
申请号：PCT/US2006/016463
申请日：2006-04-28
申请人： SIOPTICAL, INC. , DAMA, Bipin , SHASTRI, Kalpendu , PIEDE, David
发明人： DAMA, Bipin , SHASTRI, Kalpendu , PIEDE, David
IPC分类号： H04B10/12
CPC分类号： H04L25/0228 , H04B10/66 , H04L25/025 , H04L25/03057
摘要： An electronic dispersion compensation (EDC) arrangement for a multi-channel optical receive utilizes a time division technique to "share" a common adaptive algorithm block between a plurality of N separate channels. The algorithm block embodies a specific algorithm associated with correcting/updating tap weights for the delay lines forming the equalizing elements, and a time slot assignment element is used in conjunction with the algorithm block to control the access of the various channels to the algorithm block. In situations where certain channels experience a greater degree of dispersion than others, the time slot assignment element may be configured to allot a greater number of time slots to the affected channels.
摘要翻译：用于多通道光接收的电子色散补偿（EDC）装置利用时分技术“共享”多个N个独立信道之间的公共自适应算法块。算法块体现了与形成均衡元件的延迟线的校正/更新抽头权重相关联的特定算法，并且时隙分配元件与算法块结合使用以控制各种信道对算法块的访问。在某些频道经历比其他频道更大程度的色散的情况下，时隙分配元件可以被配置为向受影响的频道分配更多数量的时隙。

6. 发明申请

WO2012151520A2 WAFER SCALE PACKAGING PLATFORM FOR TRANSCEIVERS 审中-公开
标题翻译：收货机的平均包装平台
公开(公告)号：WO2012151520A2
公开(公告)日：2012-11-08
申请号：PCT/US2012/036582
申请日：2012-05-04
申请人： LIGHTWIRE LLC , SHASTRI, Kalpendu , PATEL, Vipulkumar , WEBSTER, Mark , GOTHOSKAR, Prakash , KACHRU, Ravinder , PATHAK, Soham , YELAMARTY, Rao, V. , DAUGHERTY, Thomas , DAMA, Bipin , PATEL, Kaushik , DESAI, Kishor
发明人： SHASTRI, Kalpendu , PATEL, Vipulkumar , WEBSTER, Mark , GOTHOSKAR, Prakash , KACHRU, Ravinder , PATHAK, Soham , YELAMARTY, Rao, V. , DAUGHERTY, Thomas , DAMA, Bipin , PATEL, Kaushik , DESAI, Kishor
IPC分类号： H01L25/16 , H01L25/18
CPC分类号： H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a "platform" (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
摘要翻译：光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义分离光学元件之间的光信号路径。实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

7. 发明申请

WO2006007474A2 INTEGRATED APPROACH FOR DESIGN, SIMULATION AND VERIFICATION OF MONOLITHIC, SILICON-BASED OPTO-ELECTRONIC CIRCUITS 审中-公开
标题翻译：单片硅基光电路的设计，仿真和验证综合方法
公开(公告)号：WO2006007474A2
公开(公告)日：2006-01-19
申请号：PCT/US2005022254
申请日：2005-06-22
申请人： SIOPTICAL INC , SHASTRI KALPENDU , PATHAK SOHAM , GOTHOSKAR PRAKASH , MOSINSKIS PAULIUS , DAMA BIPIN
发明人： SHASTRI KALPENDU , PATHAK SOHAM , GOTHOSKAR PRAKASH , MOSINSKIS PAULIUS , DAMA BIPIN
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product ("tape out").
摘要翻译：计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。一旦行为逻辑设计完成，结果将被合并并共同模拟。为电路中的每种不同类型的元件开发和验证物理布局设计。然后将单独的物理布局共同验证，以评估整体物理设计的属性。将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。

8. 发明申请

WO2012141828A3 OPTICAL MODULATOR UTILIZING UNARY ENCODING AND AUXILIARY MODULATOR SECTION FOR LOAD BALANCING 审中-公开
公开(公告)号：WO2012141828A3
公开(公告)日：2012-10-18
申请号：PCT/US2012/028159
申请日：2012-03-08
申请人： LIGHTWIRE LLC , METZ, Peter, C. , DAMA, Bipin , SHASTRI, Kalpendu
发明人： METZ, Peter, C. , DAMA, Bipin , SHASTRI, Kalpendu
IPC分类号： G02B6/122
摘要： An optical modulator is configured to include multiple modulating sections formed along each arm and create a unary-encoded optical output signal by driving the number of sections required to represent the data value being transmitted (e.g., three sections driven to represent the data value "3", four sections driven to represent the data value "4"). An auxiliary modulating section, isolated from the optical signal path, is included for creating a path for current flow in situations where only an odd number of modulating sections are required to represent the data. The activation of the auxiliary modulation section minimizes the current imbalance that would otherwise be present along a common node of the arrangement.

9. 发明申请

WO2006007474A3 INTEGRATED APPROACH FOR DESIGN, SIMULATION AND VERIFICATION OF MONOLITHIC, SILICON-BASED OPTO-ELECTRONIC CIRCUITS 审中-公开
公开(公告)号：WO2006007474A3
公开(公告)日：2006-01-19
申请号：PCT/US2005/022254
申请日：2005-06-22
申请人： SIOPTICAL, INC. , SHASTRI, Kalpendu , PATHAK, Soham , GOTHOSKAR, Prakash , MOSINSKIS, Paulius , DAMA, Bipin
发明人： SHASTRI, Kalpendu , PATHAK, Soham , GOTHOSKAR, Prakash , MOSINSKIS, Paulius , DAMA, Bipin
IPC分类号： G06F17/50 , G06F9/45
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: 1) digital electronic integrated circuit elements (12); 2) analog/mixed signal electronic integrated circuit elements (14); and 3) opto-electronic elements (16) (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated (18). physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified (26), to assess the properties of the overall physical design. The results of the co-simulation (18) are compared to t results of the co-verification (26), with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considere to provide a final product ("tape out").

10. 发明申请

WO2013059731A1 MOLDED GLASS LID FOR WAFER LEVEL PACKAGING OF OPTO-ELECTRONIC ASSEMBLIES 审中-公开
标题翻译：用于光伏电子组件的水平包装的模制玻璃盖
公开(公告)号：WO2013059731A1
公开(公告)日：2013-04-25
申请号：PCT/US2012/061200
申请日：2012-10-19
申请人： CISCO TECHNOLOGY, INC. , DESAI, Kishor , KACHRU, Ravinder , PATEL, Vipulkumar , DAMA, Bipin , SHASTRI, Kalpendu , PATHAK, Soham
发明人： DESAI, Kishor , KACHRU, Ravinder , PATEL, Vipulkumar , DAMA, Bipin , SHASTRI, Kalpendu , PATHAK, Soham
IPC分类号： G02B6/42 , H01L25/16
CPC分类号： G02B6/4255 , G02B6/12 , G02B6/13 , G02B6/4201 , G02B6/4257 , G02B6/4292 , G02B6/43 , H01L21/50 , H01L23/04 , H01L23/48 , H01L25/167 , H01L31/0203 , H01L33/52 , H01L2924/15311 , H01L2924/16152 , H01L2924/1616 , H01L2924/165 , H01L2924/16788 , H05K1/0268 , H05K1/0274 , H05K2201/10121 , H01L2924/0105 , H01L2924/01079
摘要： An opto-electronic assembly is provided comprising a substrate 20 (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material 22 is disposed to outline a defined peripheral area of the substrate. A molded glass lid 10 is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.
摘要翻译：提供了一种光电组件，其包括用于支撑多个互连的光学和电气部件的基底20（通常为硅或玻璃）。设置密封材料层22以概述衬底的限定的周边区域。模制玻璃盖10设置在基底上并结合到基底上，其中模制的玻璃盖被配置成产生与限定的基底周边区域匹配的覆盖区。模制玻璃盖的底表面包括一层接合材料，其在接触时与基底的密封材料层接触，形成结合组件。在一种形式中，提出了一种晶片级组装工艺，其中多个光电组件设置在硅晶片上，并且多个玻璃盖被模制在一片玻璃中，然后将其粘合到硅晶片上。

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