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1. 发明申请

US20120273845A1 ELECTRONIC PH SENSOR DIE PACKAGING 有权
标题翻译：电子PH传感器包装
公开(公告)号：US20120273845A1
公开(公告)日：2012-11-01
申请号：US13096710
申请日：2011-04-28
申请人： Gregory C. Brown , Curtis H. Rahn
发明人： Gregory C. Brown , Curtis H. Rahn
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： G01N27/414 , H01L24/24 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/15787 , H01L2924/00
摘要： A pH sensor is provided. The pH sensor comprises a substrate and an ion sensitive field effect transistor (ISFET) die comprising an ion sensing part that responds to pH, wherein the ISFET die is located over the substrate. The pH sensor also comprises a protective layer formed over at least a portion of an outer surface of the ISFET die and at least a portion of the substrate. Further, the pH sensor comprises a cover member mechanically coupled to the protective layer, wherein the cover member houses the ISFET die and the substrate, and wherein the cover member defines an opening proximate to the ion sensing part.
摘要翻译：提供pH传感器。 pH传感器包括衬底和离子敏感场效应晶体管（ISFET）管芯，其包含响应于pH的离子感测部件，其中ISFET管芯位于衬底上方。 pH传感器还包括在ISFET管芯的至少一部分外表面上形成的保护层和至少一部分基底。此外，pH传感器包括机械耦合到保护层的盖构件，其中盖构件容纳ISFET管芯和衬底，并且其中盖构件限定靠近离子感测部件的开口。

2. 发明授权

US06225178B1 Radiation hardened field oxide for VLSI sub-micron MOS device 失效
标题翻译：用于VLSI亚微米MOS器件的辐射硬化场氧化物
公开(公告)号：US06225178B1
公开(公告)日：2001-05-01
申请号：US07466709
申请日：1990-01-02
申请人： Gordon A. Shaw , Curtis H. Rahn , Cheisan Yue , Todd A. Randazzo
发明人： Gordon A. Shaw , Curtis H. Rahn , Cheisan Yue , Todd A. Randazzo
IPC分类号： H01L21336
CPC分类号： H01L21/76216
摘要： A process for oxidizing the silicon layer into a device-isolating field oxide having a radiation-hardened reduced bird's beak. An angled and rotated field implant prior to oxidation is used to increase the doping concentration in the edge region of the MOS transistors to compensate for boron leaching during oxidation. The field oxide is grown at a low temperature by high pressure oxidation which increases total dose hardness by making a silicon-rich oxide film.
摘要翻译：将硅层氧化成具有辐射硬化的还原鸟喙的装置隔离场氧化物的方法。在氧化之前使用倾斜和旋转的场注入来增加MOS晶体管的边缘区域中的掺杂浓度，以补偿氧化过程中的硼浸出。场氧化物通过高压氧化在低温下生长，通过制造富硅氧化物膜来增加总剂量硬度。

3. 发明授权

US08536626B2 Electronic pH sensor die packaging 有权
标题翻译：电子pH传感器模具包装
公开(公告)号：US08536626B2
公开(公告)日：2013-09-17
申请号：US13096710
申请日：2011-04-28
申请人： Gregory C. Brown , Curtis H. Rahn
发明人： Gregory C. Brown , Curtis H. Rahn
IPC分类号： G01N27/414
CPC分类号： G01N27/414 , H01L24/24 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/15787 , H01L2924/00
摘要： A pH sensor is provided. The pH sensor comprises a substrate and an ion sensitive field effect transistor (ISFET) die comprising an ion sensing part that responds to pH, wherein the ISFET die is located over the substrate. The pH sensor also comprises a protective layer formed over at least a portion of an outer surface of the ISFET die and at least a portion of the substrate. Further, the pH sensor comprises a cover member mechanically coupled to the protective layer, wherein the cover member houses the ISFET die and the substrate, and wherein the cover member defines an opening proximate to the ion sensing part.
摘要翻译：提供pH传感器。 pH传感器包括衬底和离子敏感场效应晶体管（ISFET）管芯，其包含响应于pH的离子感测部件，其中ISFET管芯位于衬底上方。 pH传感器还包括在ISFET管芯的至少一部分外表面上形成的保护层和至少一部分基底。此外，pH传感器包括机械耦合到保护层的盖构件，其中盖构件容纳ISFET管芯和衬底，并且其中盖构件限定靠近离子感测部件的开口。

4. 发明授权

US06952042B2 Microelectromechanical device with integrated conductive shield 失效
标题翻译：具有集成导电屏蔽的微机电装置
公开(公告)号：US06952042B2
公开(公告)日：2005-10-04
申请号：US10172865
申请日：2002-06-17
申请人： Thomas G. Stratton , Gary R. Gardner , Curtis H. Rahn
发明人： Thomas G. Stratton , Gary R. Gardner , Curtis H. Rahn
IPC分类号： B81B7/02 , B81C1/00 , G01L9/00 , G01L19/06 , H01L27/14 , H01L29/82
CPC分类号： G01L9/0042 , G01L19/0627
摘要： A microelectromechanical device and method of fabricating the same, including a layer of patterned and deposited metal or mechanical-quality, doped polysilicon inserted between the appropriate device element layers, which provides a conductive layer to prevent the microelectromechanical device's output from drifting. The conductive layer may encapsulate of the device's sensing or active elements, or may selectively cover only certain of the device's elements. Further, coupling the metal or mechanical-quality, doped polysilicon to the same voltage source as the device's substrate contact may place the conductive layer at the voltage of the substrate, which may function as a Faraday shield, attracting undesired, migrating ions from interfering with the output of the device.
摘要翻译：一种微机电装置及其制造方法，其包括插入在适当的器件元件层之间的图案化和沉积的金属或机械质量的掺杂多晶硅层，其提供导电层以防止微机电装置的输出漂移。导电层可以封装器件的感测或有源元件，或者可以选择性地仅覆盖器件的某些元件。此外，将金属或机械质量的掺杂多晶硅耦合到与器件的衬底接触相同的电压源可将导电层置于衬底的电压下，其可用作法拉第屏蔽，吸引不期望的迁移离子干扰设备的输出。

5. 发明授权

US5234861A Method for forming variable width isolation structures 失效
标题翻译：形成可变宽度隔离结构的方法
公开(公告)号：US5234861A
公开(公告)日：1993-08-10
申请号：US668013
申请日：1991-03-12
申请人： Roger L. Roisen , Curtis H. Rahn , John B. Straight , Michael S. Liu
发明人： Roger L. Roisen , Curtis H. Rahn , John B. Straight , Michael S. Liu
IPC分类号： H01L21/763
CPC分类号： H01L21/763 , Y10S438/902
摘要： An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.
摘要翻译：隔离结构以及在沉积在衬底上的有源层中使用和制造隔离结构的方法，其制造方法包括以下步骤：在邻近衬底的有源层中形成掩埋氧化物层，在衬底中形成隔离沟槽通过至少蚀刻到衬底上并且任选地进入衬底，在沟槽的暴露表面上形成介电隔离层，从沟槽的底部去除介电隔离层，并通过外延生长单晶硅形成隔离结构沟渠。

6. 发明授权

US5017999A Method for forming variable width isolation structures 失效
标题翻译：形成可变宽度隔离结构的方法
公开(公告)号：US5017999A
公开(公告)日：1991-05-21
申请号：US374960
申请日：1989-06-30
申请人： Roger L. Roisen , Curtis H. Rahn , John B. Straight , Michael S. Liu
发明人： Roger L. Roisen , Curtis H. Rahn , John B. Straight , Michael S. Liu
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/763
摘要： An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.

7. 发明申请

US20090120194A1 SILICON PRESSURE SENSOR 审中-公开
标题翻译：硅压力传感器
公开(公告)号：US20090120194A1
公开(公告)日：2009-05-14
申请号：US11937438
申请日：2007-11-08
申请人： Curtis H. Rahn , Russell L. Johnson
发明人： Curtis H. Rahn , Russell L. Johnson
IPC分类号： G01L7/08 , H01C17/28
CPC分类号： G01L9/0047 , G01L9/0054 , G01L9/06 , Y10T29/49103
摘要： A diaphragm for a pressure sensor includes a central portion having a primary thickness and a surrounding secondary portion having a secondary thickness greater than the primary thickness. The pressure sensor includes the diaphragm, a fluid conduit capped by the diaphragm, and a piezoelectric bridge for each of the primary and secondary portions to generate a signal indicative of the displacement of the portions; and a method of producing the sensor.
摘要翻译：用于压力传感器的隔膜包括具有初级厚度的中心部分和具有大于初级厚度的次级厚度的周围次级部分。压力传感器包括隔膜，由隔膜封闭的流体导管，以及用于每个初级和次级部分的压电桥，以产生指示部分位移的信号; 和传感器的制造方法。

8. 发明授权

US07514285B2 Isolation scheme for reducing film stress in a MEMS device 有权
标题翻译：用于降低MEMS器件中的膜应力的隔离方案
公开(公告)号：US07514285B2
公开(公告)日：2009-04-07
申请号：US11333015
申请日：2006-01-17
申请人： Gregory C. Brown , Curtis H. Rahn
发明人： Gregory C. Brown , Curtis H. Rahn
IPC分类号： H01L21/762
CPC分类号： B81C1/00666 , B81B2201/0264 , G01L9/0042 , G01L9/0054 , G01L19/06
摘要： A method of electrically isolating a MEMS device is provided. In one example, a piezo-resistive pressure sensor having an exposed silicon region undergoes a Local Oxidation of Silicon (LOCOS) process. An electrically insulating structure is created in the LOCOS process. The insulating structure has a rounded, or curved, interface with the piezo-resistive pressure sensor. The curved interface mitigates stresses associated with exposure to high temperatures and pressures. Additionally, the electrically insulating line may be patterned so that it has curved angles, further mitigating stress.
摘要翻译：提供了一种电隔离MEMS器件的方法。在一个示例中，具有暴露的硅区域的压阻式压力传感器经历硅的局部氧化（LOCOS）工艺。在LOCOS工艺中产生电绝缘结构。绝缘结构与压阻式压力传感器具有圆形或弯曲的界面。弯曲的界面减轻了暴露于高温和高压下的应力。此外，电绝缘线可以被图案化，使得其具有弯曲角度，进一步减轻应力。

9. 发明授权

US07381582B2 Method and structure of ion implanted elements for the optimization of resistance 有权
标题翻译：用于优化电阻的离子注入元件的方法和结构
公开(公告)号：US07381582B2
公开(公告)日：2008-06-03
申请号：US11263464
申请日：2005-10-31
申请人： Russell L. Johnson , Curtis H. Rahn
发明人： Russell L. Johnson , Curtis H. Rahn
IPC分类号： H01L21/00
CPC分类号： G01L1/2293
摘要： A method of forming a piezo-resistive sensor, comprising a piezo-resistor, a leadout resistor, and an insulator structure is provided. A Silicon-On-Insulator (SOI) substrate is provided having an epitaxial layer, a dielectric layer, and a bulk substrate layer. A mask layer is formed on top of the epitaxial layer. The mask layer defines where the piezo-resistor and leadout resistors are to be located by creating first exposed portions of the epitaxial layer. A silicon dioxide layer (SiO2) is grown in a Local Oxidation of Silicon (LOCOS) process for a predetermined time on the first exposed portions based on the desired thickness of the piezo-resistor, where the-piezo resistor is located below the SiO2 layer. The thickness of the leadout resistor, and therefore the parasitic leadout resistance, is determined by the original thickness of the epitaxial layer and can be maintained independent of the piezo-resistor thickness.
摘要翻译：提供了一种形成压电传感器的方法，包括压电电阻器，引出电阻器和绝缘体结构。提供具有外延层，电介质层和体基片层的绝缘体上硅绝缘体（SOI）衬底。掩模层形成在外延层的顶部上。掩膜层通过产生外延层的第一暴露部分来限定压电电阻器和引出电阻器将位于哪里。基于压电电阻器的期望厚度，在第一暴露部分上在局部氧化硅（LOCOS）工艺中生长二氧化硅层（SiO 2）在预定时间内，压电电阻器位于SiO 2层下方。引出电阻的厚度，因此寄生引出电阻由外延层的原始厚度确定，并且可以独立于压电电阻器厚度来保持。

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