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1. 发明申请

US20130270572A1 GROUP III-N HFET WITH A GRADED BARRIER LAYER 有权
标题翻译：具有分级障碍层的III-N组HFET
公开(公告)号：US20130270572A1
公开(公告)日：2013-10-17
申请号：US13448348
申请日：2012-04-16
申请人： David F. Brown , Miroslav Micovic
发明人： David F. Brown , Miroslav Micovic
IPC分类号： H01L29/205 , H01L21/22 , H01L21/20
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
摘要翻译：一种制造所述装置和方法，其中所述装置其中所述装置具有沉积在基板上的III族氮化物缓冲层; 和III族氮化物异质结构，其中所述III族氮化物异质结构具有III族氮化物沟道和III族氮化物阻挡层，所述III族氮化物阻挡层设置在所述III族氮化物缓冲层的表面上，氮化物沟道，III族氮化物阻挡层包括Al作为其组成III族元素之一，Al具有至少在所述III族氮化物阻挡层的一部分上变化的摩尔分数。

2. 发明申请

US20080237811A1 METHOD FOR PRESERVING PROCESSING HISTORY ON A WAFER 审中-公开
标题翻译：保存加工历史的方法
公开(公告)号：US20080237811A1
公开(公告)日：2008-10-02
申请号：US11694057
申请日：2007-03-30
申请人： Rohit Pal , David F. Brown
发明人： Rohit Pal , David F. Brown
IPC分类号： H01L23/544
CPC分类号： H01L22/20
摘要： A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region. The second partially completed feature is at a later stage of completion than the first partially completed feature.
摘要翻译：用于捕获工艺历史的方法包括至少执行用于在半导体衬底上形成特征的第一工艺。在执行第一处理之后，在半导体基板的第一区域上形成第一盖。执行至少第二过程，用于在除了第一区域之外的第二区域中形成特征，同时将第一盖留在适当位置，从而防止第一盖子覆盖的第一区域中的特征暴露于第二过程。在第一区域中测量第一特征的第一特征，并且测量第二区域中的第二特征的第二特征。晶片包括设置在第一区域中的第一部分完成特征。在第一部分完成的特征之上形成第一盖。第二部分完成的特征被布置在不同于第一区域的晶片的第二区域中。第二部分完成的功能处于完成的后期，而不是第一部分完成的功能。

3. 发明申请

US20150056764A1 Methods relating to a Group III HFET with a Graded Barrier Layer 有权
标题翻译：涉及具有梯度屏障层的III类HFET的方法
公开(公告)号：US20150056764A1
公开(公告)日：2015-02-26
申请号：US14479223
申请日：2014-09-05
申请人： David F. Brown , Miroslav Micovic
发明人： David F. Brown , Miroslav Micovic
IPC分类号： H01L29/205 , H01L29/20 , H01L29/66
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
摘要翻译：一种制造所述装置和方法，其中所述装置其中所述装置具有沉积在基板上的III族氮化物缓冲层; 和III族氮化物异质结构，其中所述III族氮化物异质结构具有III族氮化物沟道和III族氮化物阻挡层，所述III族氮化物阻挡层设置在所述III族氮化物缓冲层的表面上，氮化物沟道，III族氮化物阻挡层包括Al作为其组成III族元素之一，Al具有至少在所述III族氮化物阻挡层的一部分上变化的摩尔分数。

4. 发明授权

US08860091B2 Group III-N HFET with a graded barrier layer 有权
标题翻译：具有梯度阻挡层的III-N族HFET
公开(公告)号：US08860091B2
公开(公告)日：2014-10-14
申请号：US13448348
申请日：2012-04-16
申请人： David F. Brown , Miroslav Micovic
发明人： David F. Brown , Miroslav Micovic
IPC分类号： H01L31/072
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
摘要翻译：一种制造所述装置和方法，其中所述装置其中所述装置具有沉积在基板上的III族氮化物缓冲层; 和III族氮化物异质结构，其中所述III族氮化物异质结构具有III族氮化物沟道和III族氮化物阻挡层，所述III族氮化物阻挡层设置在所述III族氮化物缓冲层的表面上，氮化物沟道，III族氮化物阻挡层包括Al作为其组成III族元素之一，Al具有至少在所述III族氮化物阻挡层的一部分上变化的摩尔分数。

5. 发明授权

US08853709B2 III-nitride metal insulator semiconductor field effect transistor 有权
标题翻译： III族氮化物金属绝缘子半导体场效应晶体管
公开(公告)号：US08853709B2
公开(公告)日：2014-10-07
申请号：US13456039
申请日：2012-04-25
申请人： Rongming Chu , David F. Brown , Xu Chen , Adam J. Williams , Karim S. Boutros
发明人： Rongming Chu , David F. Brown , Xu Chen , Adam J. Williams , Karim S. Boutros
IPC分类号： H01L29/778 , H01L29/20
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/2006 , H01L29/205 , H01L29/4236 , H01L29/513 , H01L29/66522 , H01L29/7786 , H01L29/7787 , H01L29/78
摘要： A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.
摘要翻译：场效应晶体管（FET）包括III-氮化物沟道层，沟道层上的III-氮化物阻挡层，其中该阻挡层具有比该沟道层大的能带隙，该电极与III 氮化物层，电耦合到III族氮化物层之一的漏电极，用于将栅极电极与阻挡层电绝缘的栅极绝缘体层堆叠和沟道层，栅极绝缘体层堆叠包括绝缘体层，例如 SiN和AlN层，栅电极在源电极和漏电极之间的区域中并与绝缘体层接触，并且其中AlN层与III-氮化物层之一接触。

6. 发明授权

US3947027A High performance golf tee 失效
标题翻译：高性能高尔夫球
公开(公告)号：US3947027A
公开(公告)日：1976-03-30
申请号：US469084
申请日：1974-05-13
申请人： David F. Brown
发明人： David F. Brown
IPC分类号： A63B57/00
CPC分类号： A63B57/10
摘要： A high performance golf tee comprises a stem, a cup-shaped ball receptacle on the top of the stem, and a projection extending outwardly from the ball receptacle a sufficient distance such that when a golf ball is placed on the tee and a golf club is swung at the ball, the golf club contacts the projection and imparts motion to the ball before the golf club makes direct contact with the surface of the golf ball. The contact between the golf club and the projection imparts an initial backspin on the ball, and this improves the flight characteristics of the ball. The golf tee may be integrally molded as a unit including the projection or the projection may be formed as an attachment for a conventional golf tee.

7. 发明授权

US09525033B2 Methods relating to a group III HFET with a graded barrier layer 有权
标题翻译：涉及具有梯度阻挡层的III类HFET的方法
公开(公告)号：US09525033B2
公开(公告)日：2016-12-20
申请号：US14479223
申请日：2014-09-05
申请人： David F. Brown , Miroslav Micovic
发明人： David F. Brown , Miroslav Micovic
IPC分类号： H01L29/49 , H01L29/205 , H01L29/201 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/423
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
摘要翻译：一种制造所述装置和方法，其中所述装置其中所述装置具有沉积在基板上的III族氮化物缓冲层; 和III族氮化物异质结构，其中所述III族氮化物异质结构具有III族氮化物沟道和III族氮化物阻挡层，所述III族氮化物阻挡层设置在所述III族氮化物缓冲层的表面上，氮化物沟道，III族氮化物阻挡层包括Al作为其组成III族元素之一，Al具有至少在所述III族氮化物阻挡层的一部分上变化的摩尔分数。

8. 发明授权

US08470652B1 Monolithic integration of group III nitride enhancement layers 有权
标题翻译： III族氮化物增强层的整体整合
公开(公告)号：US08470652B1
公开(公告)日：2013-06-25
申请号：US13105706
申请日：2011-05-11
申请人： David F. Brown , Keisuke Shinohara , Miroslav Micovic , Andrea Corrion
发明人： David F. Brown , Keisuke Shinohara , Miroslav Micovic , Andrea Corrion
IPC分类号： H01L21/338
CPC分类号： H01L29/7784 , H01L21/02002 , H01L21/0254 , H01L21/02664 , H01L21/265 , H01L21/26546 , H01L21/30612 , H01L21/3081 , H01L21/8234 , H01L21/8252 , H01L27/0605 , H01L27/088 , H01L27/0883 , H01L27/095 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7783 , H03F3/211 , H03F2200/372
摘要： A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.
摘要翻译：单片集成器件包括衬底，为衬底的第一区域上的第一HFET生长的第一组III族氮化物外延层和用于在第二区域上生长的第二HFET的第二组III族氮化物外延层底物。

9. 发明授权

US4638348A Semiconductor chip carrier 失效
标题翻译：半导体芯片载体
公开(公告)号：US4638348A
公开(公告)日：1987-01-20
申请号：US595454
申请日：1984-03-30
申请人： David F. Brown , Michael J. Anstey
发明人： David F. Brown , Michael J. Anstey
IPC分类号： H01L23/12 , H01L23/498 , H01L23/538 , H01L23/02
CPC分类号： H01L23/49805 , H01L23/5385 , H01L2224/48091 , H01L2224/49109 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01019 , H01L2924/14
摘要： A circuit unit such as performing the function of a chip carrier. In one example, it is in the form of a thin square of insulating material having contact pads arranged side by side along the four edges of both major surfaces. The chip is secured substantially centrally of the insulating material and connections are made from it to the contacts on both of the major surfaces. The carrier has a lower insulating layer (5) having contacts (6) extending over its under surface and carrying the chip (14) on its upper surface. An insulating spacer (8) carries further contacts (12). Electrical connections (16 and 18) are made to the contacts (6 and 12). An insulating cover (not shown) then closes off the hollow interior, locating on a shoulder (10). The contacts (12) thus provide the contacts on the upper surface of the finished construction. A single layer construction is also disclosed. Double-sided chip carriers formed in this way are particularly suited for side-by-side mounting in racked manner, enabling maximum use to be made of the contacts on both of the major surfaces and facilitating flow of cooling air.
摘要翻译： PCT No.PCT / GB83 / 00198 Sec。 371日期1984年3月30日 102（e）1984年3月30日日期PCT提交1983年8月8日PCT公布。公开号WO84 / 00851 日期1984年3月1日。一种电路单元，例如执行芯片载体的功能。在一个示例中，它是具有绝缘材料的薄正方形的形式，其具有沿着两个主表面的四个边缘并排布置的接触垫。芯片基本上固定在绝缘材料的中央，并且连接由它制成到两个主表面上的触头。载体具有下绝缘层（5），其具有在其下表面上延伸的触点（6）并且在其上表面上承载芯片（14）。绝缘间隔件（8）承载更多的触点（12）。电连接（16和18）制成触点（6和12）。绝缘盖（未示出）然后封闭中空内部，定位在肩部（10）上。因此，触头（12）在完成的结构的上表面上提供触点。还公开了单层结构。以这种方式形成的双面芯片载体特别适用于以并排方式并排安装，从而能够最大限度地利用两个主表面上的触点并促进冷却空气的流动。

10. 发明申请

US20130026495A1 III-Nitride Metal Insulator Semiconductor Field effect Transistor 有权
标题翻译： III-Nitride金属绝缘子半导体场效应晶体管
公开(公告)号：US20130026495A1
公开(公告)日：2013-01-31
申请号：US13456039
申请日：2012-04-25
申请人： Rongming Chu , David F. Brown , Xu Chen , Adam J. Williams , Karim S. Boutros
发明人： Rongming Chu , David F. Brown , Xu Chen , Adam J. Williams , Karim S. Boutros
IPC分类号： H01L29/778 , H01L21/336 , H01L29/205
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/2006 , H01L29/205 , H01L29/4236 , H01L29/513 , H01L29/66522 , H01L29/7786 , H01L29/7787 , H01L29/78
摘要： A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.
摘要翻译：场效应晶体管（FET）包括III-氮化物沟道层，沟道层上的III-氮化物阻挡层，其中该阻挡层具有比该沟道层大的能带隙，该电极与III 氮化物层，电耦合到III族氮化物层之一的漏电极，用于将栅极电极与阻挡层电绝缘的栅极绝缘体层堆叠和沟道层，栅极绝缘体层堆叠包括绝缘体层，例如 SiN和AlN层，栅极电极在源电极和漏电极之间的区域中并与绝缘体层接触，并且其中AlN层与III-氮化物层之一接触。

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