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1. 发明授权

US09368390B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US09368390B2
公开(公告)日：2016-06-14
申请号：US13743125
申请日：2013-01-16
申请人： Chyi-Tsong Ni , I-Shi Wang , Hsin-Kuei Lee , Ching-Hou Su
发明人： Chyi-Tsong Ni , I-Shi Wang , Hsin-Kuei Lee , Ching-Hou Su
IPC分类号： H01L21/30 , H01L21/768 , H01L23/00 , B81C1/00
CPC分类号： H01L21/768 , B81B2207/012 , B81C1/00269 , B81C2203/019 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/11826 , H01L2224/11827 , H01L2224/11848 , H01L2224/13017 , H01L2224/131 , H01L2224/13562 , H01L2224/13582 , H01L2224/13624 , H01L2224/13655 , H01L2224/13657 , H01L2224/13666 , H01L2224/13669 , H01L2224/13684 , H01L2224/16145 , H01L2224/165 , H01L2224/81011 , H01L2224/81097 , H01L2224/81193 , H01L2224/81203 , H01L2224/8121 , H01L2224/81801 , H01L2224/81948 , H01L2924/00013 , H01L2924/01029 , H01L2924/01327 , H01L2924/1305 , H01L2924/1306 , H01L2924/1461 , H01L2924/01014 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer. The method further includes providing a second silicon substrate having a second contact comprising a second metal layer and placing the first contact in contact with the second contact. The method further includes heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.
摘要翻译：一种制造半导体器件的方法，包括提供具有第一接触的第一硅衬底，其中提供第一硅衬底包括在第一硅衬底和第一金属层之间形成硅化物层。该方法还包括提供第二硅衬底，其具有包括第二金属层的第二接触层，并将第一接触件与第二接触件接触。该方法还包括加热第一和第二金属层以形成金属合金，由此金属合金将第一触点与第二触点接合。

2. 发明申请

US20130130496A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130130496A1
公开(公告)日：2013-05-23
申请号：US13743125
申请日：2013-01-16
申请人： Chyi-Tsong NI , I-Shi WANG , Hsin-Kuei LEE , Ching-Hou SU
发明人： Chyi-Tsong NI , I-Shi WANG , Hsin-Kuei LEE , Ching-Hou SU
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , B81B2207/012 , B81C1/00269 , B81C2203/019 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/11826 , H01L2224/11827 , H01L2224/11848 , H01L2224/13017 , H01L2224/131 , H01L2224/13562 , H01L2224/13582 , H01L2224/13624 , H01L2224/13655 , H01L2224/13657 , H01L2224/13666 , H01L2224/13669 , H01L2224/13684 , H01L2224/16145 , H01L2224/165 , H01L2224/81011 , H01L2224/81097 , H01L2224/81193 , H01L2224/81203 , H01L2224/8121 , H01L2224/81801 , H01L2224/81948 , H01L2924/00013 , H01L2924/01029 , H01L2924/01327 , H01L2924/1305 , H01L2924/1306 , H01L2924/1461 , H01L2924/01014 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A method for fabricating a semiconductor apparatus including providing a first silicon substrate having a first contact, wherein providing the first silicon substrate comprises forming a silicide layer between the first silicon substrate and a first metal layer. The method further includes providing a second silicon substrate having a second contact comprising a second metal layer and placing the first contact in contact with the second contact. The method further includes heating the first and second metal layers to form a metallic alloy, whereby the metallic alloy bonds the first contact to the second contact.
摘要翻译：一种制造半导体器件的方法，包括提供具有第一接触的第一硅衬底，其中提供第一硅衬底包括在第一硅衬底和第一金属层之间形成硅化物层。该方法还包括提供第二硅衬底，其具有包括第二金属层的第二接触层，并将第一接触件与第二接触件接触。该方法还包括加热第一和第二金属层以形成金属合金，由此金属合金将第一触点与第二触点接合。

3. 发明授权

US07635651B2 Method of smoothening dielectric layer 有权
标题翻译：平滑电介质层的方法
公开(公告)号：US07635651B2
公开(公告)日：2009-12-22
申请号：US11208612
申请日：2005-08-23
申请人： Wen-Long Lee , Jun Wu , Shih-Chi Lin , Chyi-Tsong Ni
发明人： Wen-Long Lee , Jun Wu , Shih-Chi Lin , Chyi-Tsong Ni
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31051 , H01L21/31053
摘要： A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.
摘要翻译：一种平滑电介质层的方法。首先，提供基板。接下来，在半导体衬底上形成电介质层。最后，通过使用硅烷类气体和氮气体气体的等离子体处理使介电层平滑化。

4. 发明授权

US08643151B2 Passivation layer for semiconductor devices 有权
标题翻译：半导体器件钝化层
公开(公告)号：US08643151B2
公开(公告)日：2014-02-04
申请号：US13036897
申请日：2011-02-28
申请人： Jen-Hao Liu , Chyi-Tsong Ni , Hsiao-Yin Lin , Chung-Min Lin
发明人： Jen-Hao Liu , Chyi-Tsong Ni , Hsiao-Yin Lin , Chung-Min Lin
IPC分类号： H01L23/58
CPC分类号： H01L23/3192 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.
摘要翻译：本公开的实施例提供一种半导体器件。半导体器件包括多个金属化层，其包括最上面的金属化层。最上面的金属化层具有两个具有厚度T1并被间隙隔开的金属特征。复合钝化层包括氮化物层下的HDP CVD氧化物层。复合钝化层设置在金属特征上并部分填充间隙。复合钝化层的厚度T2约为厚度T1的20％至50％。

5. 发明申请

US20130086786A1 BONDING ALIGNMENT TOOL AND METHOD 有权
标题翻译：结合对准工具和方法
公开(公告)号：US20130086786A1
公开(公告)日：2013-04-11
申请号：US13267336
申请日：2011-10-06
申请人： Yun-Tai SHIH , Kuan-Ming PAN , Jeng-Hao LIN , I-Shi WANG , Jui-Mu CHO , Ching-Hou SU , Chyi-Tsong NI , Wun-Kai TSAI
发明人： Yun-Tai SHIH , Kuan-Ming PAN , Jeng-Hao LIN , I-Shi WANG , Jui-Mu CHO , Ching-Hou SU , Chyi-Tsong NI , Wun-Kai TSAI
IPC分类号： B23Q17/00 , B23Q15/00
CPC分类号： H01L24/75 , H01L21/67092 , H01L21/68 , H01L21/681 , H01L21/682 , H01L23/544 , H01L2223/54426 , H01L2224/75703 , H01L2224/75753 , H01L2224/75901 , Y10T29/49 , Y10T29/49002 , Y10T29/49131 , Y10T29/49764 , Y10T29/53022
摘要： An apparatus is disclosed for detecting flag velocity during a eutectic process for bonding two wafers. The apparatus includes a plurality of sensors for detecting a time and/or velocity of a plurality of flags within a flag-out mechanism. The apparatus also includes one or more displays displaying time durations associated with the movement of the flags during the bonding process. Also disclosed is a method of aligning wafers in a eutectic bonding process. The method includes determining one or more time durations associated with the movement of the flags in the plurality of flags. The method also includes determining if a misalignment has occurred based on the one or more time durations associated with the movement of the flags.
摘要翻译：公开了一种用于在用于粘合两个晶片的共晶过程期间检测标记速度的装置。该装置包括多个用于检测标志输出机构内的多个标志的时间和/或速度的传感器。该装置还包括一个或多个显示器，显示在粘合过程期间与标志的移动相关联的持续时间。还公开了一种在共晶接合工艺中对准晶片的方法。该方法包括确定与多个标志中的标志的移动相关联的一个或多个持续时间。该方法还包括基于与标志的移动相关联的一个或多个持续时间来确定是否发生了未对准。

6. 发明授权

US08378490B2 Semiconductor apparatus including a metal alloy between a first contact and a second contact 有权
标题翻译：半导体装置，包括在第一触点和第二触点之间的金属合金
公开(公告)号：US08378490B2
公开(公告)日：2013-02-19
申请号：US13048127
申请日：2011-03-15
申请人： Chyi-Tsong Ni , I-Shi Wang , Hsin-Kuei Lee , Ching-Hou Su
发明人： Chyi-Tsong Ni , I-Shi Wang , Hsin-Kuei Lee , Ching-Hou Su
IPC分类号： H01L23/48
CPC分类号： H01L21/768 , B81B2207/012 , B81C1/00269 , B81C2203/019 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/11826 , H01L2224/11827 , H01L2224/11848 , H01L2224/13017 , H01L2224/131 , H01L2224/13562 , H01L2224/13582 , H01L2224/13624 , H01L2224/13655 , H01L2224/13657 , H01L2224/13666 , H01L2224/13669 , H01L2224/13684 , H01L2224/16145 , H01L2224/165 , H01L2224/81011 , H01L2224/81097 , H01L2224/81193 , H01L2224/81203 , H01L2224/8121 , H01L2224/81801 , H01L2224/81948 , H01L2924/00013 , H01L2924/01029 , H01L2924/01327 , H01L2924/1305 , H01L2924/1306 , H01L2924/1461 , H01L2924/01014 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.
摘要翻译：提供集成电路制造的方法，更具体地说，制造具有金属合金的半导体装置。半导体器件的示例性结构包括具有第一接触的第一硅衬底，所述第一接触包括在衬底和第一金属层之间的硅化物层; 第二硅衬底，具有包括第二金属层的第二接触; 以及在第一接触件的第一金属层和第二接触件的第二金属层之间的金属合金。

7. 发明申请

US20060252258A1 Low temperature method for minimizing copper hillock defects 有权
标题翻译：用于最小化铜小丘缺陷的低温方法
公开(公告)号：US20060252258A1
公开(公告)日：2006-11-09
申请号：US11122393
申请日：2005-05-05
申请人： Jun Wu , Wen-Long Lee , Chyi-Tsong Ni , Shih-Chi Lin
发明人： Jun Wu , Wen-Long Lee , Chyi-Tsong Ni , Shih-Chi Lin
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76801 , H01L21/76883
摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200 ° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).
摘要翻译：公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。

8. 发明申请

US20060196765A1 Metallization target optimization method providing enhanced metallization layer uniformity 审中-公开
标题翻译：金属化目标优化方法提供增强的金属化层均匀性
公开(公告)号：US20060196765A1
公开(公告)日：2006-09-07
申请号：US11074524
申请日：2005-03-07
申请人： Hsi-Kuei Cheng , Chieh-Tsao Wang , Hsien-Ping Feng , Min-Yuan Cheng , Jung-Chin Tsao , Steven Lin , Ray Chuang , Chyi-Tsong NI
发明人： Hsi-Kuei Cheng , Chieh-Tsao Wang , Hsien-Ping Feng , Min-Yuan Cheng , Jung-Chin Tsao , Steven Lin , Ray Chuang , Chyi-Tsong NI
IPC分类号： C23C14/32 , C23C14/00
CPC分类号： C23C14/165 , C23C14/0641 , C23C14/0682 , C23C14/3421 , C23C14/54 , H01J37/32568 , H05K3/16
摘要： A method for forming a microelectronic layer while employing a sputtering method employs a reactor chamber. A sputtering target and a substrate are positioned within the reactor chamber, along with a sputtering target heater at a side of sputtering target opposite the substrate. At least one of: (1) a heater to sputtering target distance; (2) sputtering power; (3) deposition time; and (4) sputtering gas flow rate, is controlled in accord with a pre-determined function of sputtering target lifetime to provide enhanced uniformity of the deposited layer.
摘要翻译：采用溅射法形成微电子层的方法采用反应室。溅射靶和基板位于反应器室内，与溅射靶相对的基板上的溅射靶加热器一起。以下至少一个：（1）加热器以溅射目标距离; （2）溅射功率; （3）沉积时间; 和（4）溅射气体流速，根据溅射靶寿命的预定功能进行控制，以提供沉积层的均匀性。

9. 发明授权

US6017816A Method of fabricating A1N anti-reflection coating on metal layer 失效
标题翻译：在金属层上制造AlN防反射涂层的方法
公开(公告)号：US6017816A
公开(公告)日：2000-01-25
申请号：US805295
申请日：1997-02-25
申请人： Chyi-Tsong Ni , Kuei-Chang Tsai
发明人： Chyi-Tsong Ni , Kuei-Chang Tsai
IPC分类号： H01L21/027 , H01L21/285 , H01L21/318 , H01L21/3213 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28568 , H01L21/318 , H01L21/32137 , Y10S438/907 , Y10S438/913 , Y10S438/952
摘要： A method of fabricating notching free metal interconnection lines by utilizing aluminum nitride (AlN) as an anti-reflection coating. First, field oxide regions are formed on a semiconductor silicon wafer. Then, electrical element structures such as transistor, capacitor and resistor are formed on the predetermined area. Next, a barrier layer, a metal layer and an anti-reflection layer are successively deposited overlaying the entire silicon wafer surface. Next, the photoresist pattern is formed by the conventional lithography technique. By using photoresist pattern as an etching protection mask, the barrier layer, metal layer and anti-reflection layer are also patterned to form metal interconnection lines. Thereafter, the photoresist is stripped by oxygen plasma and sulfuric acid.
摘要翻译：一种通过利用氮化铝（AlN）作为抗反射涂层来制造无缝金属互连线的方法。首先，在半导体硅晶片上形成场氧化物区域。然后，在预定区域上形成诸如晶体管，电容器和电阻器的电气元件结构。接下来，在整个硅晶片表面上依次沉积阻挡层，金属层和抗反射层。接下来，通过常规的光刻技术形成光致抗蚀剂图案。通过使用光致抗蚀剂图案作为蚀刻保护掩模，阻挡层，金属层和抗反射层也被图案化以形成金属互连线。此后，通过氧等离子体和硫酸剥离光致抗蚀剂。

10. 发明授权

US09123754B2 Bonding alignment tool and method 有权
标题翻译：粘接对准工具及方法
公开(公告)号：US09123754B2
公开(公告)日：2015-09-01
申请号：US13267336
申请日：2011-10-06
申请人： Yun-Tai Shih , Kuan-Ming Pan , Jeng-Hao Lin , I-Shi Wang , Jui-Mu Cho , Ching-Hou Su , Chyi-Tsong Ni , Wun-Kai Tsai
发明人： Yun-Tai Shih , Kuan-Ming Pan , Jeng-Hao Lin , I-Shi Wang , Jui-Mu Cho , Ching-Hou Su , Chyi-Tsong Ni , Wun-Kai Tsai
IPC分类号： B23Q17/00 , H01L21/67 , H01L21/68
CPC分类号： H01L24/75 , H01L21/67092 , H01L21/68 , H01L21/681 , H01L21/682 , H01L23/544 , H01L2223/54426 , H01L2224/75703 , H01L2224/75753 , H01L2224/75901 , Y10T29/49 , Y10T29/49002 , Y10T29/49131 , Y10T29/49764 , Y10T29/53022
摘要： An apparatus is disclosed for detecting flag velocity during a eutectic process for bonding two wafers. The apparatus includes a plurality of sensors for detecting a time and/or velocity of a plurality of flags within a flag-out mechanism. The apparatus also includes one or more displays displaying time durations associated with the movement of the flags during the bonding process. Also disclosed is a method of aligning wafers in a eutectic bonding process. The method includes determining one or more time durations associated with the movement of the flags in the plurality of flags. The method also includes determining if a misalignment has occurred based on the one or more time durations associated with the movement of the flags.
摘要翻译：公开了一种用于在用于粘合两个晶片的共晶过程期间检测标记速度的装置。该装置包括多个用于检测标志输出机构内的多个标志的时间和/或速度的传感器。该装置还包括一个或多个显示器，显示在粘合过程期间与标志的移动相关联的持续时间。还公开了一种在共晶接合工艺中对准晶片的方法。该方法包括确定与多个标志中的标志的移动相关联的一个或多个持续时间。该方法还包括基于与标志的移动相关联的一个或多个持续时间来确定是否发生了未对准。

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