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1. 发明授权

US5291431A Array multiplier adapted for tiled layout by silicon compiler 失效
标题翻译：适用于硅编译器的平铺布局的阵列乘法器
公开(公告)号：US5291431A
公开(公告)日：1994-03-01
申请号：US965141
申请日：1992-10-22
申请人： Chung-Yih Ho , Chi-Yuan Chin , Richard I. Hartley , Michael J. Hartman , Kenneth B. Welles, II
发明人： Chung-Yih Ho , Chi-Yuan Chin , Richard I. Hartley , Michael J. Hartman , Kenneth B. Welles, II
IPC分类号： G06F7/52
CPC分类号： G06F7/5338
摘要： An array multiplier using modified Booth encoding of multiplier input signals is formed on the surface of a monolithic integrated circuit using masks generated by a computer, in accordance with a silicon compiler program, by arranging an array of standard cells selected from a library of standard cell designs in a tessellation procedure. The array multiplier is laid out in accordance with one of particular tessellation patterns, which employ simpler and more regular patterns of interconnections between cells. Carry-save addition is used in combining partial product terms to avoid concatenating long ripple carry times.
摘要翻译：使用改进的布斯编码乘法器输入信号的阵列乘法器，使用根据硅编译程序由计算机生成的掩模，在单片集成电路的表面上，通过布置从标准单元库中选择的标准单元的阵列以镶嵌程序设计。阵列乘法器根据特定的细分图案之一进行布局，其中采用更简单且更规则的单元之间的互连图案。结合部分产品术语使用保存加法来避免连接长波纹携带时间。

2. 发明授权

US5677845A Programmable data acquisition system for collecting electrical power signals 失效
标题翻译：用于收集电力信号的可编程数据采集系统
公开(公告)号：US5677845A
公开(公告)日：1997-10-14
申请号：US459861
申请日：1995-06-02
申请人： Daniel Arthur Staver , Chung-Yih Ho , Donald Thomas McGrath
发明人： Daniel Arthur Staver , Chung-Yih Ho , Donald Thomas McGrath
IPC分类号： H03M3/02 , G06F7/38 , G06F7/70
CPC分类号： H03M3/378 , H03M3/458
摘要： A programmable data acquisition system including a plurality of input signal channels for receiving a respective input signal during a normal mode of operation is provided. Individual test circuits are used for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels in the data acquisition system. An analog-to-digital (A/D) converter system, such as delta-sigma modulators and decimation filters having a selectable decimation ratio, allows for supplying quantized electrical signals at a predetermined rate. The A/D converter is responsive to any signals carried in the plurality of signal channels as selected by the individual test circuits. A control unit allows for supplying respective control signals to the test circuits and to the converter system. The data acquisition system can further include at least one feedback generating circuit for generating a measurement signal supplied to a respective one of the signal channels. This allows the data acquisition system for interfacing with a zero-flux current sensor.
摘要翻译：提供了一种可编程数据采集系统，其包括用于在正常操作模式期间接收相应输入信号的多个输入信号通道。单独的测试电路用于选择多个通道中的相应通道以在测试操作模式期间接收预定的参考信号，同时在数据采集系统中的任何剩余的未选择的通道中不间断地提供正常操作模式。诸如具有可选抽取比率的Δ-Σ调制器和抽取滤波器的模数（A / D）转换器系统允许以预定速率提供量化的电信号。 A / D转换器响应于由各个测试电路选择的多个信号通道中承载的任何信号。控制单元允许向测试电路和转换器系统提供相应的控制信号。数据采集系统还可以包括至少一个反馈产生电路，用于产生提供给相应信号通道的测量信号。这允许数据采集系统与零磁通电流传感器进行接口。

3. 发明授权

US4841467A Architecture to implement floating point multiply/accumulate operations 失效
标题翻译：架构实现浮点乘法/累加运算
公开(公告)号：US4841467A
公开(公告)日：1989-06-20
申请号：US104453
申请日：1987-10-05
申请人： Chung-Yih Ho , Karl J. Molnar , Daniel A. Staver
发明人： Chung-Yih Ho , Karl J. Molnar , Daniel A. Staver
IPC分类号： G06F7/485 , G06F7/50 , G06F7/544
CPC分类号： G06F7/485 , G06F7/5443 , G06F2207/3884 , G06F7/49936
摘要： A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.
摘要翻译：设计能够以20兆赫系统时钟速率运行的乘法/累加器芯片架构，以便以符号幅度形式接受浮点数，计算其分数部分的乘积，并将分数结果转换成二进制补码形式，以便积累与以前的产品的结果。该架构容易地以高速流水线方式计算向量式内积运算。另外，领先的零和领先的检测是以并行的方式进行的，以便从系统的添加部分快速产生后归一化结果。该系统可以在单个集成电路芯片上实现，其中存在阵列乘法器以便最小化芯片间延迟。本发明的架构提供了一种具有短流水线延迟的高速浮点乘法和累加运算。

4. 发明申请

US20050113821A1 Multi-function clamping device with stapler and ablation heads 有权
标题翻译：具有缝合器和消融头的多功能夹紧装置
公开(公告)号：US20050113821A1
公开(公告)日：2005-05-26
申请号：US10721303
申请日：2003-11-25
申请人： Rajesh Pendekanti , Shailendra Parihar , Chung-Yih Ho
发明人： Rajesh Pendekanti , Shailendra Parihar , Chung-Yih Ho
IPC分类号： A61B17/00 , A61B17/072 , A61B18/14 , A61B17/08
CPC分类号： A61B17/072 , A61B17/068 , A61B18/1442 , A61B2017/00477 , A61B2017/07221 , A61B2017/2945 , A61B2018/1432 , A61B2018/145 , A61B2018/1495
摘要： Stapler and ablation clamping heads can be interchangeably coupled to a hand-operated actuation mechanism using a quick connect/quick release coupling. In the actuation mechanism, a first user-operable lever controls clamping of the jaws of either head, while a second user-operable lever controls the firing of staples in the stapler head. A removable staple holder may be used with the stapler head to allow easy reloading of staples as well as the use of different sizes and type of staples. A corresponding removable anvil may be used as well. A removable electrode holder may be used with the ablation head to allow the use of different electrode configurations. Moreover, a removable electrode holder may be used over the jaws of a stapler head as an overlay.
摘要翻译：订书机和消融夹头可以使用快速连接/快速释放联接器互换地连接到手动操作的致动机构。在致动机构中，第一用户可操作的杆控制任一头的夹爪的夹持，而第二用户可操作的杆控制订书机头中的钉的点火。可以使用可拆卸的订书钉保持器与订书机头一起使用，以便能够容易地重新装载订书钉以及使用不同尺寸和类型的订书钉。也可以使用相应的可拆卸的砧座。消除头可以使用可拆卸的电极夹，以允许使用不同的电极构造。此外，可以在装订器头的钳口上使用可移除电极保持器作为覆盖层。

5. 发明授权

US5799211A Shift register having latch cell operable in serial-in/parallel-out and parallel-in/serial-out modes in response to a sequence of commands for controlling appropriate switches 失效
标题翻译：移位寄存器具有响应于用于控制适当开关的一系列命令的以串并入/并行输出和并行/串行输出模式操作的锁存单元
公开(公告)号：US5799211A
公开(公告)日：1998-08-25
申请号：US621020
申请日：1996-03-22
申请人： Juka Mikko Hakkarainen , Nga Cheung Lee , Chung-Yih Ho
发明人： Juka Mikko Hakkarainen , Nga Cheung Lee , Chung-Yih Ho
IPC分类号： G11C7/10 , G11C19/00 , G11C19/28 , G06F5/00
CPC分类号： G11C19/28 , G11C19/00 , G11C7/1036
摘要： A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.
摘要翻译：配置为在ASIC环境中实现的通信单元仅使用少量的芯片表面积并且需要最小数量的引脚。该单元相对于ASIC内部时钟异步工作，使得通信可以独立于这种内部时钟发生。在一个实施例中，通信单元包括经由数据总线耦合到移位寄存器的控制器。与控制器的引脚连接包括请求线REQ，输入/输出控制线I / O（或INOUT），确认线ACK，外部时钟线EXTCLK和数据线DATA。移位寄存器还经由数据总线耦合到存储器模块，例如RAM。 ASIC处理器通过控制线耦合到控制器，移位寄存器和存储器模块。

6. 发明授权

US5973582A Resonance imager mobile van magnetic field homogeneity shift compensation 失效
标题翻译：共振成像机移动面包车磁场均匀性移位补偿
公开(公告)号：US5973582A
公开(公告)日：1999-10-26
申请号：US195128
申请日：1998-11-18
申请人： Timothy John Havens , Chung-Yih Ho , Xianrui Huang , Steven Ho-Chong Wong , Bu-Xin Xu , Minfeng Xu
发明人： Timothy John Havens , Chung-Yih Ho , Xianrui Huang , Steven Ho-Chong Wong , Bu-Xin Xu , Minfeng Xu
IPC分类号： H01F6/00 , G01R33/3873 , H01F7/00
CPC分类号： G01R33/3873
摘要： In the installation of a superconducting magnet for magnetic resonance imaging at a preselected position in a mobile van, preselected curvilinear magnetic segments are applied to preselected locations on the exterior of the magnet to counteract magnet inhomogeneities in the imaging bore which would otherwise occur because of magnetic material in the van structure.
摘要翻译：在用于在移动式货车中的预选位置安装用于磁共振成像的超导磁体的情况下，将预选的曲线磁段施加到磁体外部的预选位置以抵消成像孔中的磁体不均匀性，否则将由于磁性而发生货车结构材料。

7. 发明授权

US07431720B2 Multi-function clamping device with stapler and ablation heads 有权
标题翻译：具有缝合器和消融头的多功能夹紧装置
公开(公告)号：US07431720B2
公开(公告)日：2008-10-07
申请号：US10721303
申请日：2003-11-25
申请人： Rajesh Pendekanti , Shailendra K. Parihar , Chung-Yih Ho
发明人： Rajesh Pendekanti , Shailendra K. Parihar , Chung-Yih Ho
IPC分类号： A61B18/12
CPC分类号： A61B17/072 , A61B17/068 , A61B18/1442 , A61B2017/00477 , A61B2017/07221 , A61B2017/2945 , A61B2018/1432 , A61B2018/145 , A61B2018/1495
摘要： Stapler and ablation clamping heads can be interchangeably coupled to a hand-operated actuation mechanism using a quick connect/quick release coupling. In the actuation mechanism, a first user-operable lever controls clamping of the jaws of either head, while a second user-operable lever controls the firing of staples in the stapler head. A removable staple holder may be used with the stapler head to allow easy reloading of staples as well as the use of different sizes and type of staples. A corresponding removable anvil may be used as well. A removable electrode holder may be used with the ablation head to allow the use of different electrode configurations. Moreover, a removable electrode holder may be used over the jaws of a stapler head as an overlay.
摘要翻译：订书机和消融夹头可以使用快速连接/快速释放联接器互换地连接到手动操作的致动机构。在致动机构中，第一用户可操作的杆控制任一头的夹爪的夹持，而第二用户可操作的杆控制订书机头中的钉的点火。可以使用可拆卸的订书钉保持器与订书机头一起使用，以便能够容易地重新装载订书钉以及使用不同尺寸和类型的订书钉。也可以使用相应的可拆卸的砧座。消除头可以使用可拆卸的电极夹，以允许使用不同的电极构造。此外，可以在装订器头的钳口上使用可移除电极保持器作为覆盖层。

8. 发明授权

US6119175A On-chip communication circuit and protocol for microcontroller-based ASICs 失效
标题翻译：用于基于微控制器的ASIC的片上通信电路和协议
公开(公告)号：US6119175A
公开(公告)日：2000-09-12
申请号：US093531
申请日：1998-06-08
申请人： Juka Mikko Hakkarainen , Nga Cheung Lee , Chung-Yih Ho
发明人： Juka Mikko Hakkarainen , Nga Cheung Lee , Chung-Yih Ho
IPC分类号： G11C7/10 , G11C19/00 , G11C19/28 , G06F12/00
CPC分类号： G11C19/28 , G11C19/00 , G11C7/1036
摘要： A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.
摘要翻译：配置为在ASIC环境中实现的通信单元仅使用少量的芯片表面积并且需要最小数量的引脚。该单元相对于ASIC内部时钟异步工作，使得通信可以独立于这种内部时钟发生。在一个实施例中，通信单元包括经由数据总线耦合到移位寄存器的控制器。与控制器的引脚连接包括请求线REQ，输入/输出控制线I / O（或INOUT），确认线ACK，外部时钟线EXTCLK和数据线DATA。移位寄存器还经由数据总线耦合到存储器模块，例如RAM。 ASIC处理器通过控制线耦合到控制器，移位寄存器和存储器模块。

9. 发明授权

US5212392A Optical sensing apparatus for detecting linear displacement of an object and method of operation thereof with detector matrix and centroid detection 失效
标题翻译：用于检测物体的线性位移的光学感测装置及其检测器矩阵和质心检测的操作方法
公开(公告)号：US5212392A
公开(公告)日：1993-05-18
申请号：US806507
申请日：1991-12-13
申请人： Ertugrul Berkcan , Chung-Yih Ho , Jerome J. Tiemann , Fathy F. Yassa
发明人： Ertugrul Berkcan , Chung-Yih Ho , Jerome J. Tiemann , Fathy F. Yassa
IPC分类号： G01D5/30
CPC分类号： G01D5/30
摘要： Apparatus for sensing linear displacement of an object between first and second locations along an axis is used to sense conditions that can be made to vary displacement of an object in accordance with the condition, such as temperature, pressure and rotary motion. A light beam projected along an incident light path to the object is reflected along a reflective light path by a reflector affixed to the object. A photo-sensor array in the reflective light path intercepts the reflected light beam and produces samples of the intensity of the reflected image at multiple positions along a line across the array. An imager coupled to the array converts the light samples to representative electrical samples. The resultant light intensity information is provided to an electronic processor which determines a first centroid of the reflected image when the object is at a first location and a second centroid when the object is at a second location, and employs the difference between the first and second centroids to determine the displacement of the object.
摘要翻译：用于感测沿着轴线的第一和第二位置之间物体的线性位移的装置用于感测可以根据诸如温度，压力和旋转运动等条件改变物体的位移的条件。沿着入射光路投射到物体的光束被反射光路通过固定在物体上的反射体反射。反射光路中的光电传感器阵列截取反射光束，并沿着阵列的一条线的多个位置产生反射图像强度的样本。耦合到阵列的成像器将光样本转换成代表性的电样品。所得到的光强度信息被提供给电子处理器，该电子处理器当物体处于第一位置时确定反射图像的第一质心，并且当物体处于第二位置时确定第二质心，并且采用第一和第二质心来确定物体的位移。

10. 发明授权

US4901263A Versatile data shifter with sticky bit generation capability 失效
标题翻译：具有粘性位生成功能的多功能数据移位器
公开(公告)号：US4901263A
公开(公告)日：1990-02-13
申请号：US243359
申请日：1988-09-12
申请人： Chung-Yih Ho , Karl J. Molnar , Daniel A. Staver
发明人： Chung-Yih Ho , Karl J. Molnar , Daniel A. Staver
IPC分类号： G06F5/01
CPC分类号： G06F5/012 , G06F7/49952
摘要： A barrel-shift data shifter structure is modified to segregate switches in a switching matrix included therein into those switches as participate in a simple shift as well as in a barrel shift and those switches used only in a barrel shift. The former set of switches is controlled by shift control signals alone, and the latter set of switches responds to shift control signals and to the presence or absence of a rotation enable signal. The number of switches required is substantially smaller than required in a barrel shifter followed in cascade by a simple data shifter. Preferably provision is made for sticky bit generation. The sticky bit is the LOGIC OR response to all bits shifted to less significance than output data.
摘要翻译：修改桶形移位数据移位器结构以将其中包括的开关矩阵中的开关分离为参与简单移位以及桶位移动的那些开关，以及仅在桶形移位中使用的开关。前一组开关由单独的换档控制信号控制，后一组开关响应换档控制信号以及是否有旋转使能信号。所需的开关数量明显小于桶形移位器中所需的开关数量，然后由简单的数据移位器级联。优选地设置用于产生粘性位。粘性位是对所有位的LOGIC OR响应移位到比输出数据更小的意义。

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