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1. 发明授权

US09012967B2 1T MIM memory for embedded RAM application in soc 有权
标题翻译： 1T MIM存储器，用于soc中的嵌入式RAM应用
公开(公告)号：US09012967B2
公开(公告)日：2015-04-21
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L27/108 , H01L29/94 , H01L27/02
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

2. 发明申请

US20120139022A1 1T MIM MEMORY FOR EMBEDDED RAM APPLICATION IN SOC 审中-公开
标题翻译： 1T MIM存储器嵌入式RAM应用于SOC
公开(公告)号：US20120139022A1
公开(公告)日：2012-06-07
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L29/92 , H01L27/108
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

3. 发明授权

US5196357A Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor 失效
标题翻译：制造扩展多晶硅自对准栅极重叠轻微掺杂漏极结构的方法，用于亚微米晶体管
公开(公告)号：US5196357A
公开(公告)日：1993-03-23
申请号：US793916
申请日：1991-11-18
申请人： William J. Boardman , Ying T. Loh , Edward D. Nowak , Chung S. Wang
发明人： William J. Boardman , Ying T. Loh , Edward D. Nowak , Chung S. Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66606
摘要： For a structure with an overlapping gate region, a first insulator layer is placed on a substrate. A source/drain polysilicon layer is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer is placed on the source/drain polysilicon layer. A gap is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region is formed in the gap and extends over the source/drain polysilicon layer. The gate polysilicon region is separated from the source/drain polysilicon layer and the polysilicon filler regions by a dielectric region. Source/drain regions are formed by atoms in the source/drain polysilicon layer diffusing through the polysilicon filler regions into the substrate.
摘要翻译：对于具有重叠栅极区域的结构，将第一绝缘体层放置在基板上。源极/漏极多晶硅层放置在绝缘体层上。源极/漏极多晶硅层掺杂有第一导电类型的原子。在源极/漏极多晶硅层上放置第二绝缘体层。在第二绝缘体层和源极/漏极多晶硅层中蚀刻间隙以暴露第一绝缘体层的一部分。蚀刻第一绝缘体层的暴露部分和附加量的第二绝缘体下面的第一绝缘体层，以便扩大间隙并切割源/漏多晶硅层的一部分。形成两个多晶硅填料区，其填充包括源/漏多晶硅层下面的底切区的间隙的一部分。栅极多晶硅区域形成在间隙中并在源极/漏极多晶硅层上延伸。栅极多晶硅区域通过电介质区域与源极/漏极多晶硅层和多晶硅填充区域分离。源/漏区由源极/漏极多晶硅层中的原子形成，通过多晶硅填料区扩散到衬底中。

4. 发明授权

US4574177A Plasma etch method for TiO.sub.2 失效
标题翻译： TiO2 + B等离子体蚀刻法
公开(公告)号：US4574177A
公开(公告)日：1986-03-04
申请号：US671027
申请日：1984-11-13
申请人： Chung S. Wang
发明人： Chung S. Wang
IPC分类号： H01L21/311 , H01L31/18 , B23K9/00
CPC分类号： H01L31/1884 , H01L21/31116 , Y02E10/50
摘要： A method for plasma etching of TiO.sub.2, using a mixture of oxygen and a fluorine-bearing species, preferably CF.sub.4. This mixture gives good selectivity over aluminum and photoresist, and approximately unity selectivity over silica or silicon nitride. Use of a chlorine-containing species is also taught by the invention, and will provide different selectivities. The present invention is also useful for etching in the RIE mode.
摘要翻译：使用氧和含氟物质的混合物，优选CF 4等离子体蚀刻TiO 2的方法。该混合物对铝和光致抗蚀剂具有良好的选择性，并且对二氧化硅或氮化硅具有大致一致的选择性。本发明还教导了含氯物质的使用，并将提供不同的选择性。本发明也可用于RIE模式中的蚀刻。

5. 发明授权

US4521446A Method for depositing polysilicon over TiO.sub.2 失效
标题翻译：在TiO2上沉积多晶硅的方法
公开(公告)号：US4521446A
公开(公告)日：1985-06-04
申请号：US557382
申请日：1983-11-30
申请人： Donald J. Coleman, Jr. , Roger A. Haken , Chung S. Wang
发明人： Donald J. Coleman, Jr. , Roger A. Haken , Chung S. Wang
IPC分类号： H01L21/02 , H01L21/3205 , H01L29/51 , H01L21/316
CPC分类号： H01L29/517 , H01L21/32055 , H01L28/40
摘要： Hydrogen annealing permits deposition of good quality polysilicon atop TiO.sub.2. Hydrogen annealing of TiO.sub.2 prevents the tremendous hydrogen affinity of as-deposited TiO.sub.2 from disrupting process reactions during deposition of polysilicon.
摘要翻译：氢退火允许在TiO 2顶部沉积优质多晶硅。二氧化钛的氢退火可防止沉积二氧化钛在多晶硅沉积过程中破坏工艺反应的巨大氢亲和力。

6. 发明授权

US5496751A Method of forming an ESD and hot carrier resistant integrated circuit structure 失效
标题翻译：形成ESD和耐热承载集成电路结构的方法
公开(公告)号：US5496751A
公开(公告)日：1996-03-05
申请号：US394064
申请日：1995-02-24
申请人： Yi-Hen Wei , Ying T. Loh , Chung S. Wang , Chenming Hu
发明人： Yi-Hen Wei , Ying T. Loh , Chung S. Wang , Chenming Hu
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/7836
摘要： An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate. A method of the present invention includes the steps of providing a semiconductor substrate, forming a gate over the substrate to define a channel, doping the substrate to form a pair of LDD regions in the substrate, doping the region to form a drain region and a source region, and doping the substrate to form a drain-side DDD region in the substrate which substantially separates the drain region from a drain-side LDD region and which substantially isolates the drain region from a bulk portion of the substrate, and to form a source-side DDD region in the substrate which substantially separates the source region from a source-side LDD region and substantially isolates the source region from a bulk portion of the substrate.
摘要翻译：一种集成电路器件，包括衬底，形成在衬底上的栅极结构，形成在栅极下方的衬底中的沟道，在衬底中与漏极侧相邻形成的轻掺杂漏极侧LDD区（优选地，通过LATID工艺），形成在衬底附近的漏极侧LDD区域的漏极区域和将漏极侧LDD区域与漏极区域基本上分离的漏极侧DDD区域。优选地，集成电路器件被对称地形成为使得在与衬底的源极侧相邻的衬底（再次优选地通过LATID工艺）中形成轻掺杂的源极侧LDD区，源极区形成在在源极侧LDD区域附近形成基板，在基板上形成源极侧DDD区域，以使源极侧LDD区域与源极区域大致分离。更优选地，DDD区域基本上将源极和漏极与基板的主体部分隔离。本发明的方法包括以下步骤：提供半导体衬底，在衬底上形成栅极以限定通道，掺杂衬底以在衬底中形成一对LDD区域，掺杂该区域以形成漏区和源极区域，并且掺杂衬底以在衬底中形成漏极侧DDD区域，其基本上将漏极区域与漏极侧LDD区域分离，并且基本上将漏极区域与衬底的本体部分隔离，并形成源极侧DDD区域，其基本上将源极区域与源极侧LDD区域分离开来并且基本上将源极区域与衬底的主体部分隔离。

7. 发明授权

US5340761A Self-aligned contacts with gate overlapped lightly doped drain (goldd) structure 失效
标题翻译：自对准触点与栅极重叠轻掺杂漏极（goldd）结构
公开(公告)号：US5340761A
公开(公告)日：1994-08-23
申请号：US786321
申请日：1991-10-31
申请人： Ying T. Loh , Chung S. Wang
发明人： Ying T. Loh , Chung S. Wang
IPC分类号： H01L21/285 , H01L21/336 , H01L21/28
CPC分类号： H01L29/6659 , H01L21/28518 , H01L29/6656
摘要： In a method for producing a transistor with an overlapping gate region, a gate region is placed on a substrate between two source/drain regions. Spacers are placed around the gate region. The spacers are formed of dielectric material. A thin layer of polysilicon is deposited over the two source/drain regions and over electrically insulating regions adjacent to the two source/drain regions. Portions of the thin layer of polysilicon are oxidized to electrically isolate the two source/drain regions. A metal-silicide layer is formed on the portions of the thin layer of polysilicon which are not oxidized. The metal-silicide layer is connected to a metal layer. The electrical contact of the metal-silicide layer and the metal layer is over an electrically insulating layer.
摘要翻译：在用于制造具有重叠栅极区域的晶体管的方法中，栅极区域被放置在两个源极/漏极区域之间的衬底上。隔板放置在门区周围。间隔物由电介质材料形成。在两个源极/漏极区域和与两个源极/漏极区域相邻的电绝缘区域上沉积薄层多晶硅。多晶硅薄层的一部分被氧化以电隔离两个源极/漏极区域。在未被氧化的多晶硅薄层的部分上形成金属硅化物层。金属硅化物层连接到金属层。金属硅化物层和金属层的电接触在电绝缘层之上。

8. 发明授权

US5288652A BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure 失效
标题翻译： BICMOS兼容方法，用于创建具有横向渐变发射极结构的双极晶体管
公开(公告)号：US5288652A
公开(公告)日：1994-02-22
申请号：US993229
申请日：1992-12-18
申请人： Chung S. Wang , Ying-Tsong Loh , Edward D. Nowak
发明人： Chung S. Wang , Ying-Tsong Loh , Edward D. Nowak
IPC分类号： H01L21/8249 , H01L21/265 , H01L29/70
CPC分类号： H01L21/8249 , Y10S438/944
摘要： A bipolar transistor is fabricated in a CMOS-compatible process with a laterally graded emitter structure that is fabricated in a "top-down" implant process. The laterally graded emitter decreases electric field intensities in the emitter-base junction under reverse bias, thus reducing hot carrier generation and improving emitter-base junction breakdown voltage. High current gain is further maintained by establishing sharply defined emitter-base junctions. During fabrication a blocking layer and overlying cap layer are formed in an inverted "T" shape over a desired emitter window region. Lateral projection of the cap ledges are used to define the laterally graded emitter width, while the distance separating the cap ledges defines the width of the central emitter region. The central emitter region is implanted and driven-in to a desired depth, after which the protective cap is removed. The entire emitter window region is then implanted with a like polarity dopant of lesser dosage, which dopant is then driven-in to form laterally graded emitter junctions of a desired depth. A BiCMOS integrated circuit may be fabricated with bipolar transistors of either polarity and with MOS transistors of either polarity, using substantially the same process steps. The resultant MOS devices have lightly doped drain regions to enhance MOS hot carrier performance.
摘要翻译：双极晶体管以CMOS兼容工艺制造，具有以“自顶向下”注入工艺制造的横向渐变发射极结构。横向渐变发射极在反向偏压下降低发射极 - 基极结中的电场强度，从而减少热载流子的产生并改善发射极 - 基极结击穿电压。通过建立清晰的发射极 - 基极结，进一步维持高电流增益。在制造期间，在期望的发射器窗口区域上以倒置的“T”形状形成阻挡层和覆盖覆盖层。盖凸缘的横向投影用于限定横向渐变发射器宽度，而分隔盖凸缘的距离限定了中心发射极区域的宽度。将中心发射极区域植入并驱动到期望的深度，之后去除保护盖。然后用较小剂量的类似极性掺杂剂注入整个发射极窗口区域，然后将该掺杂剂驱入以形成期望深度的横向渐变的发射极结。可以使用基本上相同的工艺步骤，制造具有任一极性的双极晶体管和任一极性的MOS晶体管的BiCMOS集成电路。所得的MOS器件具有轻掺杂漏极区以增强MOS热载体性能。

9. 发明授权

US08148223B2 1T MIM memory for embedded ram application in soc 有权
标题翻译： 1T MIM存储器，用于嵌入式RAM应用
公开(公告)号：US08148223B2
公开(公告)日：2012-04-03
申请号：US11437673
申请日：2006-05-22
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

10. 发明授权

US5444003A Method and structure for creating a self-aligned bicmos-compatible bipolar transistor with a laterally graded emitter structure 失效
标题翻译：用于产生具有横向渐变发射极结构的自对准二元双极晶体管的方法和结构
公开(公告)号：US5444003A
公开(公告)日：1995-08-22
申请号：US81761
申请日：1993-06-23
申请人： Chung S. Wang , Ying-Tsong Loh , Ho-Yuan Yu
发明人： Chung S. Wang , Ying-Tsong Loh , Ho-Yuan Yu
IPC分类号： H01L21/8249 , H01L27/06 , H01L21/265 , H01L21/70 , H01L27/00 , H01L21/255
CPC分类号： H01L27/0623 , H01L21/8249
摘要： A bipolar transistor is fabricated in a CMOS-compatible process so as to be self-aligning, with resultant small geometry and improved high frequency performance, and to have improved hot carrier characteristics. The bipolar device has a laterally graded emitter structure that is fabricated in a "top-down" implant process. During fabrication sidewall spacers are formed overlying the peripheral region of the laterally graded emitter. These spacers protect the underlying region against counter-doping during a subsequent intrinsic base implant, and cause the emitter and base contacts to be self-aligning. Because bipolar dimensions are thus reduced, a very narrow base width is achieved, resulting in improved device cutoff frequency. Further, a narrower emitter-base contact separation is achieved, reducing junction area and attendant junction capacitance. A base link region is formed to further improve emitter-base breakdown voltage, and to reduce extrinsic base resistance. A BiCMOS integrated circuit may be fabricated with bipolar transistors of either polarity and with MOS transistors of either polarity. BiCMOS fabrication can occur wherein substantially the same process steps are employed, or wherein specific bipolar and MOS implant steps are decoupled to optimize laterally graded emitter dopant profiles, base-link resistance, and MOS off-state leakage currents.
摘要翻译：双极晶体管以CMOS兼容工艺制造，以便进行自对准，从而获得小的几何形状和改善的高频性能，并具有改进的热载流子特性。双极器件具有横向渐变的发射极结构，其以“自顶向下”植入工艺制造。在制造期间，侧壁间隔物形成在横向渐变发射体的周边区域上。这些间隔件在随后的本征基极植入期间保护底层区域免受反掺杂，并且使发射极和基极触点自对准。因为双极尺寸因此减小，所以实现非常窄的基极宽度，导致器件截止频率的提高。此外，实现较窄的发射极 - 基极接触分离，减少结面积和伴随的结电容。形成基极连接区域以进一步提高发射极 - 基极击穿电压，并减少外部基极电阻。 BiCMOS集成电路可以用任一极性的双极晶体管和任一极性的MOS晶体管制造。可以发生BiCMOS制造，其中采用基本上相同的工艺步骤，或者其中特定的双极和MOS注入步骤被去耦以优化横向渐变的发射极掺杂物分布，基极连接电阻和MOS截止状态漏电流。

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