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1. 发明申请

US20120271986A1 Flash Memory Device and Data Protection Method Thereof 有权
标题翻译：闪存设备及其数据保护方法
公开(公告)号：US20120271986A1
公开(公告)日：2012-10-25
申请号：US13453452
申请日：2012-04-23
申请人： Chun-Yi LO , Hsu-Ping OU
发明人： Chun-Yi LO , Hsu-Ping OU
IPC分类号： G06F12/00
CPC分类号： G06F12/14 , G06F12/0246 , G06F2212/1052 , G06F2212/202
摘要： A data protection method for a flash memory device. In one embodiment, the flash memory device comprises a flash memory for storing protected data. After the flash memory device is coupled to a host, a plurality of current read addresses of a plurality of read commands sent from the host to the flash memory device are recorded. The current read addresses are then compared with a plurality of predetermined read addresses. When the current read addresses are not identical to the predetermined read addresses, the flash memory device is made to enter a data protection mode. When the flash memory device is in the data protection mode, if the flash memory device receives a plurality of data access commands, the data access commands are processed according to a protection mode setting parameter to prevent the protected data from being accessed by the host.
摘要翻译：一种闪存设备的数据保护方法。在一个实施例中，闪存设备包括用于存储受保护数据的闪存。在闪速存储器件耦合到主机之后，记录从主机发送到闪存器件的多个读取命令的多个当前读取地址。然后将当前的读取地址与多个预定的读取地址进行比较。当当前的读取地址与预定的读取地址不同时，使闪存设备进入数据保护模式。当闪存设备处于数据保护模式时，如果闪速存储设备接收到多个数据访问命令，则根据保护模式设置参数处理数据访问命令，以防止主机访问受保护的数据。

2. 发明授权

US10497120B2 Method and apparatus of fiber tracking, and non-transitory computer-readable medium thereof 有权
公开(公告)号：US10497120B2
公开(公告)日：2019-12-03
申请号：US15953456
申请日：2018-04-15
申请人： Ching-Po Lin , Shin-Tai Chong , Chun-Yi Lo , Chu-Chung Huang
发明人： Ching-Po Lin , Shin-Tai Chong , Chun-Yi Lo , Chu-Chung Huang
IPC分类号： G06K9/00 , G06T7/00 , A61B6/03 , A61B6/00
CPC分类号： G06T7/0016 , A61B6/032 , A61B6/501 , A61B6/506 , G06T2207/10081 , G06T2207/10088 , G06T2207/30016
摘要： The present disclosure illustrates a method and an apparatus of fiber tracking, and non-transitory computer-readable medium thereof. In an embodiment, a fiber tracking process is performed on a diffusion magnetic resonance image of a subject's brain based on validated and better tracking parameters, so as to obtain first tracking images, nerve fibers between two first regions of interest in each of the first tracking images are extracted, a nerve fasciculus skeleton is established based on an overlapping process performed on the plurality of nerve fibers extracted from the first tracking images, and the nerve fibers more similar to the structure of the nerve fasciculus skeleton are selected to obtain a specific fasciculus of the subject. Thus, the technical solution of the present disclosure can be used to improve the sensitivity of fiber tracking and be useful for improvement of preoperative assessment and surgical navigation.

3. 发明授权

US08838884B2 Flash memory device and data protection method thereof 有权
标题翻译：闪存设备及其数据保护方法
公开(公告)号：US08838884B2
公开(公告)日：2014-09-16
申请号：US13453452
申请日：2012-04-23
申请人： Chun-Yi Lo , Hsu-Ping Ou
发明人： Chun-Yi Lo , Hsu-Ping Ou
IPC分类号： G06F12/00 , G06F12/02 , G06F12/14
CPC分类号： G06F12/14 , G06F12/0246 , G06F2212/1052 , G06F2212/202
摘要： A data protection method for a flash memory device. In one embodiment, the flash memory device comprises a flash memory for storing protected data. After the flash memory device is coupled to a host, a plurality of current read addresses of a plurality of read commands sent from the host to the flash memory device are recorded. The current read addresses are then compared with a plurality of predetermined read addresses. When the current read addresses are not identical to the predetermined read addresses, the flash memory device is made to enter a data protection mode. When the flash memory device is in the data protection mode, if the flash memory device receives a plurality of data access commands, the data access commands are processed according to a protection mode setting parameter to prevent the protected data from being accessed by the host.
摘要翻译：一种闪存设备的数据保护方法。在一个实施例中，闪存设备包括用于存储受保护数据的闪存。在闪速存储器件耦合到主机之后，记录从主机发送到闪存器件的多个读取命令的多个当前读取地址。然后将当前的读取地址与多个预定的读取地址进行比较。当当前的读取地址与预定的读取地址不同时，使闪存设备进入数据保护模式。当闪存设备处于数据保护模式时，如果闪速存储设备接收到多个数据访问命令，则根据保护模式设置参数处理数据访问命令，以防止主机访问受保护的数据。

4. 发明授权

US08479132B2 Active trace assertion based verification system 有权
标题翻译：基于主动跟踪断言的验证系统
公开(公告)号：US08479132B2
公开(公告)日：2013-07-02
申请号：US11455134
申请日：2006-06-16
申请人： Kuen-Yang Tsai , Yung-Chuan Chen , Chun-Yi Lo
发明人： Kuen-Yang Tsai , Yung-Chuan Chen , Chun-Yi Lo
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A computer processes simulation data indicating values of circuit signals as functions of simulation time to determine whether a circuit exhibits a property defined by an assertion. The assertion expresses the property as a sequence of expressions, each a function of one or more variables, where each variable represents a value of one or more signals or a value of another sequence of expressions. The assertion statement separately defines an evaluation time for each expression, a particular simulation time at which the expression is to be evaluated. Each expression must evaluate true if the circuit has the property. The computer produces a display including a representation of each expression of the property including a separate variable symbol for each of its variables. For each expression that evaluated false, the computer identifies each variable that caused that expression to evaluate false and distinctively marks that variable's symbol relative to other variable symbols within the display. For each expression that evaluated true, the computer identifies the evaluation time contributing the fulfillment of assertion property. The computer also annotates the representation of each expression with its corresponding evaluation time and annotates each displayed variable symbol with a value of the variable it represents.
摘要翻译：计算机处理指示电路信号值作为模拟时间的函数的模拟数据，以确定电路是否呈现由断言定义的属性。断言将属性表示为表达式序列，每个表达式是一个或多个变量的函数，其中每个变量表示一个或多个信号的值或另一个表达式序列的值。断言语句分别定义每个表达式的评估时间，表达式将被评估的特定模拟时间。如果电路具有属性，则每个表达式必须评估为真。计算机产生一个显示器，其中包括该属性的每个表达式的表示，包括每个变量的单独变量符号。对于评估为false的每个表达式，计算机标识导致该表达式评估为false的每个变量，并显着地标记该变量的符号相对于显示内的其他变量符号。对于评估为true的每个表达式，计算机识别有助于实现断言属性的评估时间。计算机还用相应的评估时间对每个表达式的表示进行注释，并用其表示的变量的值来注释每个显示的变量符号。

5. 发明申请

US20070294651A1 Active trace assertion based verification system 有权
标题翻译：基于主动跟踪断言的验证系统
公开(公告)号：US20070294651A1
公开(公告)日：2007-12-20
申请号：US11455134
申请日：2006-06-16
申请人： Kuen-Yang Tsai , Yung-Chuan Chen , Chun-Yi Lo
发明人： Kuen-Yang Tsai , Yung-Chuan Chen , Chun-Yi Lo
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A computer processes simulation data indicating values of circuit signals as functions of simulation time to determine whether a circuit exhibits a property defined by an assertion. The assertion expresses the property as a sequence of expressions, each a function of one or more variables, where each variable represents a value of one or more signals or a value of another sequence of expressions. The assertion statement separately defines an evaluation time for each expression, a particular simulation time at which the expression is to be evaluated. Each expression must evaluate true if the circuit has the property. The computer produces a display including a representation of each expression of the property including a separate variable symbol for each of its variables. For each expression that evaluated false, the computer identifies each variable that caused that expression to evaluate false and distinctively marks that variable's symbol relative to other variable symbols within the display. For each expression that evaluated true, the computer identifies the evaluation time contributing the fulfillment of assertion property. The computer also annotates the representation of each expression with its corresponding evaluation time and annotates each displayed variable symbol with a value of the variable it represents.
摘要翻译：计算机处理指示电路信号值作为模拟时间的函数的模拟数据，以确定电路是否呈现由断言定义的属性。断言将属性表示为表达式序列，每个表达式是一个或多个变量的函数，其中每个变量表示一个或多个信号的值或另一个表达式序列的值。断言语句分别定义每个表达式的评估时间，表达式将被评估的特定模拟时间。如果电路具有属性，则每个表达式必须评估为真。计算机产生一个显示器，其中包括该属性的每个表达式的表示，包括每个变量的单独变量符号。对于评估为false的每个表达式，计算机标识导致该表达式评估为false的每个变量，并显着地标记该变量的符号相对于显示内的其他变量符号。对于评估为true的每个表达式，计算机识别有助于实现断言属性的评估时间。计算机还用相应的评估时间对每个表达式的表示进行注释，并用其表示的变量的值来注释每个显示的变量符号。

6. 发明申请

US20190318480A1 METHOD AND APPARATUS OF FIBER TRACKING, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM THEREOF 审中-公开
公开(公告)号：US20190318480A1
公开(公告)日：2019-10-17
申请号：US15953456
申请日：2018-04-15
申请人： Ching-Po LIN , Shin-Tai CHONG , Chun-Yi LO , Chu-Chung HUANG
发明人： Ching-Po LIN , Shin-Tai CHONG , Chun-Yi LO , Chu-Chung Huang
IPC分类号： G06T7/00 , A61B6/03 , A61B6/00
摘要： The present disclosure illustrates a method and an apparatus of fiber tracking, and non-transitory computer-readable medium thereof. In an embodiment, a fiber tracking process is performed on a diffusion magnetic resonance image of a subject's brain based on validated and better tracking parameters, so as to obtain first tracking images, nerve fibers between two first regions of interest in each of the first tracking images are extracted, a nerve fasciculus skeleton is established based on an overlapping process performed on the plurality of nerve fibers extracted from the first tracking images, and the nerve fibers more similar to the structure of the nerve fasciculus skeleton are selected to obtain a specific fasciculus of the subject. Thus, the technical solution of the present disclosure can be used to improve the sensitivity of fiber tracking and be useful for improvement of preoperative assessment and surgical navigation.

7. 发明授权

US08949504B2 Memory devices and memory control methods with ISP code 有权
标题翻译：内存设备和内存控制方式与ISP代码
公开(公告)号：US08949504B2
公开(公告)日：2015-02-03
申请号：US13621493
申请日：2012-09-17
申请人： Wei-Lun Yan , Chun-Yi Lo
发明人： Wei-Lun Yan , Chun-Yi Lo
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： A memory device is provided, including a first memory die, a second memory die and a controller. The first memory die has a first system block. The second memory die has a second system block. The controller is coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, in which, when the memory device is turned on, the controller reads the ISP code from the first system block or the second system block.
摘要翻译：提供了一种存储器件，包括第一存储器管芯，第二存储器管芯和控制器。第一个存储器管芯具有第一个系统块。第二存储器管芯具有第二系统块。控制器通过芯片使能通道耦合到第一和第二存储器管芯，以便将相同的在系统编程代码（ISP代码）写入第一和第二系统块，其中当存储器件被打开时，控制器从第一个系统块或第二个系统块读取ISP代码。

8. 发明申请

US20140013063A1 Memory Devices and Memory Control Methods 有权
标题翻译：内存设备和内存控制方法
公开(公告)号：US20140013063A1
公开(公告)日：2014-01-09
申请号：US13621493
申请日：2012-09-17
申请人： Wei-Lun Yan , Chun-Yi Lo
发明人： Wei-Lun Yan , Chun-Yi Lo
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： A memory device is provided, including a first memory die, a second memory die and a controller. The first memory die has a first system block. The second memory die has a second system block. The controller is coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, in which, when the memory device is turned on, the controller reads the ISP code from the first system block or the second system block.
摘要翻译：提供了一种存储器件，包括第一存储器管芯，第二存储器管芯和控制器。第一个存储器管芯具有第一个系统块。第二存储器管芯具有第二系统块。控制器通过芯片使能通道耦合到第一和第二存储器管芯，以便将相同的在系统编程代码（ISP代码）写入第一和第二系统块，其中当存储器件被打开时，控制器从第一个系统块或第二个系统块读取ISP代码。

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