会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明申请
    • VARIABLE DELAY CIRCUIT AND DELAY-LOCKED LOOP INCLUDING THE SAME
    • 可变延迟电路和延迟锁定环路,包括它们
    • US20110216864A1
    • 2011-09-08
    • US13035093
    • 2011-02-25
    • Chul Woo KimYoung Ho Kwak
    • Chul Woo KimYoung Ho Kwak
    • H04L7/00
    • H04L7/00
    • The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
    • 本公开提供了一种可变延迟电路,包括延迟电路,该延迟电路包括第一延迟单元和第二延迟单元,并延迟输入信号以产生输出信号; 选择信号生成单元,其检测所述延迟电路的延迟值,并生成选择信号,以选择用于延迟来自所述第一延迟单元和所述第二延迟单元的输入信号的延迟单元; 第一控制单元,响应于延迟增减信号,控制由选择信号选择的延迟单元的延迟值; 以及第二控制单元,其控制未被选择信号选择的延迟单元的延迟值。
    • 10. 发明申请
    • Frequency Multiplier
    • 频率乘数
    • US20090189652A1
    • 2009-07-30
    • US11659023
    • 2005-07-27
    • Chul-Woo KimJin-Han KimSeok-Ryung YoonYoung-Ho KwakSeok-Soo Yoon
    • Chul-Woo KimJin-Han KimSeok-Ryung YoonYoung-Ho KwakSeok-Soo Yoon
    • H03B19/00
    • G06F7/68
    • A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.
    • 公开了一种倍频器。 多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个,调节第一和第二公共节点处的电压电平。 输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。 输出缓冲器调节输出节点处的电压电平,并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。 在输入来自压控延迟线的每个输入信号的上升沿之前,放电电路对第一节点放电。 在输入来自压控延迟线的每个输入信号的上升沿之前,充电电路对第二节点充电。