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    • 3. 发明申请
    • VARIABLE DELAY CIRCUIT AND DELAY-LOCKED LOOP INCLUDING THE SAME
    • 可变延迟电路和延迟锁定环路,包括它们
    • US20110216864A1
    • 2011-09-08
    • US13035093
    • 2011-02-25
    • Chul Woo KimYoung Ho Kwak
    • Chul Woo KimYoung Ho Kwak
    • H04L7/00
    • H04L7/00
    • The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
    • 本公开提供了一种可变延迟电路,包括延迟电路,该延迟电路包括第一延迟单元和第二延迟单元,并延迟输入信号以产生输出信号; 选择信号生成单元,其检测所述延迟电路的延迟值,并生成选择信号,以选择用于延迟来自所述第一延迟单元和所述第二延迟单元的输入信号的延迟单元; 第一控制单元,响应于延迟增减信号,控制由选择信号选择的延迟单元的延迟值; 以及第二控制单元,其控制未被选择信号选择的延迟单元的延迟值。
    • 10. 发明授权
    • Variable delay circuit and delay-locked loop including the same
    • 可变延迟电路和延迟锁定环路包括相同
    • US08451970B2
    • 2013-05-28
    • US13035093
    • 2011-02-25
    • Chul Woo KimYoung Ho Kwak
    • Chul Woo KimYoung Ho Kwak
    • H03D3/24H04L7/00H04L25/40H03L7/06H03L7/00
    • H04L7/00
    • The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
    • 本公开提供了一种可变延迟电路,包括延迟电路,该延迟电路包括第一延迟单元和第二延迟单元,并延迟输入信号以产生输出信号; 选择信号生成单元,其检测所述延迟电路的延迟值,并生成选择信号,以选择用于延迟来自所述第一延迟单元和所述第二延迟单元的输入信号的延迟单元; 第一控制单元,响应于延迟增减信号,控制由选择信号选择的延迟单元的延迟值; 以及第二控制单元,其控制未被选择信号选择的延迟单元的延迟值。