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1. 发明授权

US09464212B2 Adhesive composition and optical member using the same 有权
标题翻译：粘合剂组合物和使用其的光学构件
公开(公告)号：US09464212B2
公开(公告)日：2016-10-11
申请号：US13241307
申请日：2011-09-23
申请人： Woo Jin Jeong , Chul Jeong , Ri Ra Jung , Hee Yeon Ki
发明人： Woo Jin Jeong , Chul Jeong , Ri Ra Jung , Hee Yeon Ki
IPC分类号： C09J133/06 , C08L33/06 , C09J7/02
CPC分类号： C09J7/0246 , C08L33/06 , C09J7/22 , C09J7/38 , C09J133/06 , C09J2201/622 , C09J2203/318 , C09J2433/00 , Y10T428/28
摘要： An adhesive composition and an optical member using the same, the adhesive composition providing an adhesive having a storage modulus of about 8×105 to about 1×108 dyne/cm2 and a gel fraction of about 83% to about 95% as defined by Equation 1: Gel fraction (%)=(A/B)×100, [Equation 1] in Equation 1, A is a mass measured after dissolving the adhesive at 23° C. for 48 hours in a solvent and then drying for 24 hours, and B is an initial mass.

2. 发明授权

US09152213B2 Bus system in SoC and method of gating root clocks therefor 有权
标题翻译： SoC中的总线系统和门控时钟的方法
公开(公告)号：US09152213B2
公开(公告)日：2015-10-06
申请号：US13556545
申请日：2012-07-24
申请人： Jaegeun Yun , Lingling Liao , Bub-chul Jeong
发明人： Jaegeun Yun , Lingling Liao , Bub-chul Jeong
IPC分类号： G06F1/32 , G06F1/10 , G06F13/40
CPC分类号： G06F13/4291 , G06F1/10 , G06F1/3237 , G06F13/28 , G06F13/364 , G06F13/405 , G06F13/4054 , G06F2213/0038 , Y02B70/12 , Y02B70/123 , Y02D10/128 , Y02D10/151
摘要： A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.
摘要翻译：一种片上系统总线系统，包括：总线，被配置为将片上系统的功能块彼此连接;以及时钟门控单元，连接到总线的接口单元，并且被配置为基本上对在根据事务检测信号的状态来操作安装在总线上的总线桥装置。

3. 发明授权

US08570710B2 Multilayered ceramic electronic component 有权
标题翻译：多层陶瓷电子元件
公开(公告)号：US08570710B2
公开(公告)日：2013-10-29
申请号：US13356320
申请日：2012-01-23
申请人： Jong Han Kim , Hyun Chul Jeong
发明人： Jong Han Kim , Hyun Chul Jeong
IPC分类号： H01G4/06
CPC分类号： H01G4/005 , H01G4/12 , H01G4/30
摘要： There is provided multilayered ceramic electronic component having a 0603 size or less, the multilayered ceramic electronic component including: a ceramic body including a plurality of internal electrodes and dielectric layers disposed between the internal electrodes; and external electrodes disposed on outer surfaces of the ceramic body and electrically connected to the internal electrodes, wherein when a region in which the internal electrodes are overlapped is defined as an active region in a cross section of a central portion in a length direction of the ceramic body, taken in width and thickness directions thereof, the entire area of the cross section taken in the width and thickness directions is defined as At, and an area of the active region is defined as Aa, the following equation is satisfied: 65%≦Aa/At≦90%.
摘要翻译：提供具有0603尺寸以下的多层陶瓷电子部件，所述多层陶瓷电子部件包括：陶瓷体，包括设置在所述内部电极之间的多个内部电极和电介质层; 以及设置在所述陶瓷体的外表面并与内部电极电连接的外部电极，其中，当内部电极重叠的区域被定义为在所述内部电极的长度方向上的中心部分的截面中的有源区域陶瓷体的宽度方向和厚度方向的截面宽度和厚度方向的整个面积被定义为At，有源区域的面积被定义为Aa，满足下式：65％ @Aa / At @ 90％。

4. 发明申请

US20130193948A1 LOW POWER CIRCUIT FOR REDUCING LEAKAGE POWER USING NEGATIVE VOLTAGE 有权
标题翻译：用于降低泄漏电力的低功率电路使用负电压
公开(公告)号：US20130193948A1
公开(公告)日：2013-08-01
申请号：US13680040
申请日：2012-11-17
申请人： Jae Sup LEE , Seong Joong KIM , Bum Man KIM , Han-Kyu LEE , Dae-Chul JEONG , Tae Young CHUNG
发明人： Jae Sup LEE , Seong Joong KIM , Bum Man KIM , Han-Kyu LEE , Dae-Chul JEONG , Tae Young CHUNG
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , H03K17/063 , H03K2017/066
摘要： A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.
摘要翻译：提供了使用负电压降低漏电功率的电源电路。电源电路包括电流源，其包括包括栅极的晶体管。电源电路还包括连接到晶体管的栅极的电流源控制电路，并且被配置为如果电流源以工作模式工作，则向晶体管的栅极施加正电压，并将负电压施加到如果电流源要在非活动模式下工作，晶体管的栅极。

5. 发明授权

US08443122B2 Asynchronous upsizing circuit in data processing system 有权
标题翻译：数据处理系统中的异步升压电路
公开(公告)号：US08443122B2
公开(公告)日：2013-05-14
申请号：US12917854
申请日：2010-11-02
申请人： JaeGeun Yun , Junhyung Um , Woo-Cheol Kwon , Hyun-Joon Kang , Bub-chul Jeong
发明人： JaeGeun Yun , Junhyung Um , Woo-Cheol Kwon , Hyun-Joon Kang , Bub-chul Jeong
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4059
摘要： An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.
摘要翻译：数据处理系统中的异步增大电路。异步升压电路包括异步封隔器和异步解包器。异步封隔器包括通常用于异步桥的写入缓冲器，并且用于增大和缓冲写通道数据; 以及第一和第二异步打包控制器，分别根据第一和第二时钟控制在突发写入操作期间输入/输出到写入缓冲器的写入通道数据的通道压缩。异步解包器包括通常用于异步网桥的读缓冲器，并用于增大和缓冲读通道数据; 以及分别针对在突发读取操作期间从读取缓冲器输入/输出的读通道数据，分别根据第一和第二时钟控制信道压缩的第一和第二异步解包控制器。

6. 发明申请

US20130112338A1 METHOD OF MANUFACTURING MULTILAYER CERAMIC CAPACITOR 审中-公开
标题翻译：制造多层陶瓷电容器的方法
公开(公告)号：US20130112338A1
公开(公告)日：2013-05-09
申请号：US13610343
申请日：2012-09-11
申请人： Young Ho Kim , Jong Han Kim , Hyun Chul Jeong
发明人： Young Ho Kim , Jong Han Kim , Hyun Chul Jeong
IPC分类号： H01G13/00
CPC分类号： H01G4/30 , B32B18/00 , C04B35/6263 , C04B2235/612 , C04B2237/32 , H01G4/1209 , H01G4/2325 , Y10T156/1052
摘要： There is provided a method of manufacturing a multilayer ceramic capacitor including: laminating ceramic green sheets having internal electrodes printed thereon to form a ceramic laminated body; cutting the ceramic laminated body; applying slurry including a ceramic powder to the ceramic laminated body; and drying the slurry applied to the ceramic laminated body. According to an embodiment of the present invention, cracks generated in a manufacturing process of the multilayer ceramic capacitor may be removed, such that the multilayer ceramic capacitor may have excellent reliability.
摘要翻译：提供一种制造多层陶瓷电容器的方法，包括：层叠印刷有内部电极的陶瓷生片以形成陶瓷层叠体; 切割陶瓷层压体; 将包含陶瓷粉末的浆料涂覆到陶瓷层叠体上; 并干燥施加到陶瓷层压体上的浆料。根据本发明的实施例，可以去除在多层陶瓷电容器的制造过程中产生的裂纹，使得多层陶瓷电容器可以具有优异的可靠性。

7. 发明申请

US20130063862A1 MULTILAYER CERAMIC ELECTRONIC COMPONENT AND FABRICATION METHOD THEREOF 有权
标题翻译：多层陶瓷电子元件及其制造方法
公开(公告)号：US20130063862A1
公开(公告)日：2013-03-14
申请号：US13333359
申请日：2011-12-21
申请人： Jong Han KIM , Hyun Chul Jeong , Jae Man Park
发明人： Jong Han KIM , Hyun Chul Jeong , Jae Man Park
IPC分类号： H01G4/008 , B32B38/14
CPC分类号： H01G4/30 , H01G4/005
摘要： There is provided a multilayer ceramic electronic component, including: a ceramic main body including a dielectric layer; and inner electrodes disposed to face each other within the ceramic main body, with the dielectric layer interposed therebetween, wherein, when an average thickness of the dielectric layer is td and an average thickness of the inner electrodes is te, 0.1 μm≦te≦0.5 μm and (td+te)/te≦2.5 are satisfied, and when an average surface roughness on a virtual surface roughness center line of the inner electrode is Ra and an average roughness of ten points of the inner electrode is Rz, 5 nm≦Ra≦30 nm, 150 nm≦Rz≦td/2, and 8≦Rz/Ra≦20 are satisfied. The multilayer ceramic electronic component has excellent reliability by improving adhesion strength between the dielectric layer and the inner electrodes and withstand voltage characteristics.
摘要翻译：提供了一种多层陶瓷电子部件，包括：包括电介质层的陶瓷主体; 以及在陶瓷主体内部彼此相对配置的内部电极，介电层插入其间，其中，当电介质层的平均厚度为td，内部电极的平均厚度为te时，为0.1μm＆lt; lE; te＆nlE; 0.5 并且当内部电极的虚拟表面粗糙度中心线上的平均表面粗糙度为Ra并且内部电极的10个点的平均粗糙度为Rz时，为5nm＆amp; nlE;并且（td + te）/te＆ Ra和nlE; 30nm，150nm和nlE; Rz＆amp; NlE; td / 2和8＆nlE; Rz / Ra＆nlE; 20。多层陶瓷电子部件通过提高介电层与内部电极之间的粘合强度和耐电压特性而具有优异的可靠性。

8. 发明申请

US20130049532A1 CERAMIC ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：陶瓷电子元件及其制造方法
公开(公告)号：US20130049532A1
公开(公告)日：2013-02-28
申请号：US13333220
申请日：2011-12-21
申请人： Jong Han KIM , Hyun Chul Jeong
发明人： Jong Han KIM , Hyun Chul Jeong
IPC分类号： H01L41/00 , H01C7/10 , B32B37/06 , H01G4/12 , B32B37/14 , H01C7/13 , H01F5/00
CPC分类号： H01G4/30 , H01C7/1006 , H01C7/13 , H01C7/18 , H01G4/0085 , H01G4/12
摘要： There are provided a ceramic electronic component and a method of manufacturing the same. The ceramic electronic component includes: a ceramic element; and an internal electrode layer formed within the ceramic element, having a thickness of 0.5 μm or less, and including anon-electrode region formed therein, wherein an area ratio of the non-electrode region to an electrode region of the internal electrode layer, in a cross section of the internal electrode layer is between 0.1% and 10%, and the non-electrode region includes a ceramic component.
摘要翻译：提供陶瓷电子部件及其制造方法。陶瓷电子部件包括：陶瓷元件; 以及形成在所述陶瓷元件内的内部电极层，其厚度为0.5μm以下，并且包括形成在其中的阳极区域，其中所述非电极区域与所述内部电极层的电极区域的面积比，内部电极层的截面为0.1％〜10％，非电极区域为陶瓷成分。

9. 发明申请

US20120215955A1 System on Chip Comprising Interconnector and Control Method Thereof 有权
标题翻译：系统芯片组成互连器及其控制方法
公开(公告)号：US20120215955A1
公开(公告)日：2012-08-23
申请号：US13396155
申请日：2012-02-14
申请人： Jaegeun Yun , Sung-Min Hong , Bub-chul Jeong
发明人： Jaegeun Yun , Sung-Min Hong , Bub-chul Jeong
IPC分类号： G06F13/00
CPC分类号： G06F13/1657
摘要： A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.
摘要翻译：片上系统包括多个主设备，响应于多个主设备的请求提供数据的多个从设备和配置成以流水线方式顺次处理来自多个主设备的请求的指针更新逻辑。

10. 发明申请

US20110187961A1 DISPLAY APPARATUS 有权
标题翻译：显示设备
公开(公告)号：US20110187961A1
公开(公告)日：2011-08-04
申请号：US13082429
申请日：2011-04-08
申请人： Hyun-chul Jeong , Jae-hwan Chun , Jong-ho Won , Sung-won Chung , Jung-ki Kim , Sang-sun Han , Yu-kwan Kim , Jeong-ki Kim
发明人： Hyun-chul Jeong , Jae-hwan Chun , Jong-ho Won , Sung-won Chung , Jung-ki Kim , Sang-sun Han , Yu-kwan Kim , Jeong-ki Kim
IPC分类号： G02F1/1333
CPC分类号： G06F1/1601 , H04N5/645
摘要： A display apparatus includes a display module and a front case. The display module displays images. The display module includes a boss fixing member having a combination hole. The front case covers a first surface of the display module and has a first boss that is inserted into the combination hole to combine the front case to the display module. The first boss is formed at inside edges of the display module. The boss fixing member is positioned within the edges of the display module which define the outdimension of the display module.
摘要翻译：显示装置包括显示模块和前壳。显示模块显示图像。显示模块包括具有组合孔的凸台固定构件。前壳体覆盖显示模块的第一表面，并且具有插入组合孔中的第一凸台，以将前壳体与显示模块组合。第一凸台形成在显示模块的内边缘处。凸台固定构件位于显示模块的边缘内，其限定显示模块的尺寸。

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