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2. 发明授权

US4523975A Integrated circuit planarizing process 失效
标题翻译：集成电路平面化处理
公开(公告)号：US4523975A
公开(公告)日：1985-06-18
申请号：US372690
申请日：1982-04-28
申请人： Christopher K. Groves , Kevin Duncan , Edward C. D. Darwall
发明人： Christopher K. Groves , Kevin Duncan , Edward C. D. Darwall
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L23/52
CPC分类号： H01L21/31055 , H01L21/31116 , H01L21/312 , H01L21/76819
摘要： A planarizing process for producing a passivation or insulating layer immediately underlying an upper metallized layer on the surface of an integrated circuit having very large radius of curvature steps, thus providing a reliable base for the metallized layer. The process is comprised of the steps of depositing and defining first metal conductors on the surface of an integrated circuit, depositing a first dielectric layer over the surface of the integrated circuit including the conductors, the dielectric layer being comprised of material selected from the group comprised of silicon dioxide and silicon nitride, depositing and polymerizing a layer of negative isoprene resist over the surface of the dielectric layer, plasma etching the surface of the isoprene and dielectric layers to a predetermined thickness over the metal conductors in an atmosphere of CF.sub.4 gas containing 32 to 50% oxygen, cleaning the etched surface, and depositing a second dielectric layer over the surface selected from a group comprised of silicon dioxide and silicon nitride, whereby a surface having very large radius of curvature steps over the metal conductors is produced.
摘要翻译：一种平面化工艺，用于在具有非常大的曲率半径的集成电路的表面上产生刚好位于上部金属化层下方的钝化层或绝缘层，从而为金属化层提供可靠的基底。该方法包括以下步骤：在集成电路的表面上沉积和限定第一金属导体，在包括导体的集成电路的表面上沉积第一介电层，介电层由选自以下的材料组成：的二氧化硅和氮化硅，在电介质层的表面上沉积和聚合一层负的异戊二烯抗蚀剂，在包含32的CF 4气体的气氛中，将异戊二烯和电介质层的表面等离子体蚀刻到金属导体上的预定厚度至50％的氧气，清洁蚀刻表面，以及在从由二氧化硅和氮化硅组成的组中选择的表面上沉积第二介质层，由此产生具有非常大的曲率半径的表面在金属导体上方的表面。

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