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1. 发明申请

US20130200934A1 DUTY CYCLE ADJUSTMENT CIRCUIT 有权
标题翻译：占空比调整电路
公开(公告)号：US20130200934A1
公开(公告)日：2013-08-08
申请号：US13367777
申请日：2012-02-07
申请人： Juergen Hertle , Christian I. Menolfi , Thomas H. Toifl
发明人： Juergen Hertle , Christian I. Menolfi , Thomas H. Toifl
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.
摘要翻译：占空比调整电路包括时钟信号输入节点; 时钟信号输出节点; 耦合到所述时钟信号输入节点的控制电压产生电路; 以及第一反相器，被配置为接收包括在时钟信号输入节点处接收的输入时钟信号和从控制电压产生电路接收的控制电压之和的反相器输入信号，并且在时钟信号输出端输出输出时钟信号节点，其中所述控制电压的变化被配置为改变所述输出时钟信号的占空比。

2. 发明授权

US08466722B2 Startup and protection circuitry for thin oxide output stage 有权
标题翻译：薄氧化物输出级的启动和保护电路
公开(公告)号：US08466722B2
公开(公告)日：2013-06-18
申请号：US13284265
申请日：2011-10-28
申请人： Marcel A. Kossel , Daihyun Lim , Christian I. Menolfi , Pradeep Thiagarajan
发明人： Marcel A. Kossel , Daihyun Lim , Christian I. Menolfi , Pradeep Thiagarajan
IPC分类号： H03L7/00
CPC分类号： H01L27/0266
摘要： A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.
摘要翻译：一种用于启动和操作发射机的输出级的方法，所述输出级包括第一保护场效应晶体管（FET）和第二保护FET，使能启动电路; 向所述输出级中的所述第一保护FET提供第一偏置电压，以及通过所述启动电路向所述输出级中的所述第二保护FET级提供第二偏置电压; 禁用启动电路并启用保护电压发生器; 通过保护电压发生器向输出级中的第一保护FET提供第一偏置电压; 以及通过第二偏置电压电源在所述输出级中向所述第二保护FET提供所述第二偏置电压。

3. 发明申请

US20090060091A1 LOW-POWER, LOW-AREA HIGH-SPEED RECEIVER ARCHITECTURE 有权
标题翻译：低功率，低地区高速接收机架构
公开(公告)号：US20090060091A1
公开(公告)日：2009-03-05
申请号：US11848599
申请日：2007-08-31
申请人： Christoph Hagleitner , Christian I. Menolfi , Martin L. Schmatz , Thomas H. Toifl
发明人： Christoph Hagleitner , Christian I. Menolfi , Martin L. Schmatz , Thomas H. Toifl
IPC分类号： H04L27/00
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/091 , H03L7/10 , H04L7/0008
摘要： A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.
摘要翻译：高速接收机包括多个接收机组件。每个接收器组件包括用于接收数据的采样锁存器，用于控制由采样锁存器采样数据的定时的相位旋转器以及用于提供时钟和数据恢复的时钟跟踪逻辑级。时钟跟踪逻辑级分为高速早/晚（E / L）逻辑和聚合计数器部分以及由同步逻辑块分隔的低速逻辑部分。接收机还包括用于接收对应于接收数据的数据速率的输入时钟信号的延迟锁定环路（DLL），提供时钟信号的粗略的延迟调整，并将对应于经调整的时钟信号的多个时钟相位矢量输出到相位每个接收器组件上的旋转器。相位旋转器基于从DLL接收的时钟相位矢量来控制数据的采样。单个稳压电源调节器调节提供给DLL和相位旋转器的电源。

4. 发明申请

US20080175344A1 Low Jitter Communication System 有权
标题翻译：低抖动通信系统
公开(公告)号：US20080175344A1
公开(公告)日：2008-07-24
申请号：US11961545
申请日：2007-12-20
申请人： Christian I. Menolfi , Martin Leo Schmatz , Thomas H. Tolfi
发明人： Christian I. Menolfi , Martin Leo Schmatz , Thomas H. Tolfi
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H03L7/07 , H03L7/08 , H03L7/0805 , H04L7/0037
摘要： The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by means of the delayed jitter signal.
摘要翻译：所述通信系统具有发射机和接收机，其中所述发射机和所述接收机通过时钟信道和数据信道耦合，其中所述时钟信道比所述数据信道短，并且其中所述接收机包括用于提取抖动信号的延迟电路从时钟信道信号延迟提取的抖动信号，并通过延迟的抖动信号产生接收机的接收机时钟信号。

5. 发明授权

US08917762B2 Receiver with four-slice decision feedback equalizer 有权
标题翻译：接收机采用四片判决反馈均衡器
公开(公告)号：US08917762B2
公开(公告)日：2014-12-23
申请号：US13486644
申请日：2012-06-01
申请人： Pier A. Francese , Christian I. Menolfi , Thomas H. Toifl
发明人： Pier A. Francese , Christian I. Menolfi , Thomas H. Toifl
IPC分类号： H04L27/06 , H04L25/03
CPC分类号： H04L25/03146 , H04L2025/03484
摘要： A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.
摘要翻译：用于接收机的判决反馈均衡器（DFE）片包括多个非投机DFE抽头; 和3个推测性DFE抽头，其中3个推测性DFE抽头包括第一和第二多路复用器级，第一和第二多路复用器级中的每一个包括4个比较器锁存器，4个比较器锁存器中的每一个具有可编程偏移量; 以及多路复用器，其从4个比较器锁存器接收4个比较器锁存器输出并输出多路复用器级输出，其中多路复用器由先前的符号决定dn-2和dn-3控制; 并且其中所述3个推测抽头还包括2：1判决复用器级，其接收所述第一和第二多路复用器级的多路复用器级输出，并由先前的符号判定dn-1控制以输出片输出信号dn。

6. 发明授权

US08170157B2 Low jitter communication system 有权
标题翻译：低抖动通信系统
公开(公告)号：US08170157B2
公开(公告)日：2012-05-01
申请号：US11961545
申请日：2007-12-20
申请人： Christian I. Menolfi , Martin Leo Schmatz , Thomas H. Toifl
发明人： Christian I. Menolfi , Martin Leo Schmatz , Thomas H. Toifl
IPC分类号： H04L27/08
CPC分类号： H04L7/0008 , H03L7/07 , H03L7/08 , H03L7/0805 , H04L7/0037
摘要： The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by the delayed jitter signal.
摘要翻译：所述通信系统具有发射机和接收机，其中所述发射机和所述接收机通过时钟信道和数据信道耦合，其中所述时钟信道比所述数据信道短，并且其中所述接收机包括用于提取抖动信号的延迟电路从时钟信道信号延迟提取的抖动信号，并通过延迟的抖动信号产生接收机的接收机时钟信号。

7. 发明申请

US20090039916A1 Systems and Apparatus for Providing a Multi-Mode Memory Interface 审中-公开
标题翻译：用于提供多模式存储器接口的系统和装置
公开(公告)号：US20090039916A1
公开(公告)日：2009-02-12
申请号：US11834926
申请日：2007-08-07
申请人： Peter Buchmann , Christian I. Menolfi , Martin L. Schmatz , Thomas H. Toifl , Jonas R. Weiss
发明人： Peter Buchmann , Christian I. Menolfi , Martin L. Schmatz , Thomas H. Toifl , Jonas R. Weiss
IPC分类号： G06F7/38
CPC分类号： G11C7/1045 , G11C5/066 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/109
摘要： An integrated circuit for a memory input/output (I/O) pin has five different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. A T-coil circuit equalizes the capacitive loading of the high-speed functions. An exemplary embodiment provides a memory chip containing a multi-functional physical I/O circuit that can act as power or ground; as a DDR2 or DDR3 interface; as a high-speed differential receiver; or as a high-speed differential transmitter.
摘要翻译：用于存储器输入/输出（I / O）引脚的集成电路具有五种不同的操作模式。内存芯片可以使用无缓冲（或注册）双列直插式内存模块（DIMM）以及完全缓冲的DIMM进行操作。 T型线圈电路可以均衡高速功能的电容负载。示例性实施例提供了包含可用作电源或接地的多功能物理I / O电路的存储器芯片; 作为DDR2或DDR3接口; 作为高速差分接收机; 或作为高速差分变送器。

8. 发明申请

US20090002082A1 MULTIPHASE SIGNAL GENERATOR 有权
标题翻译：多相信号发生器
公开(公告)号：US20090002082A1
公开(公告)日：2009-01-01
申请号：US11962681
申请日：2007-12-21
申请人： Christian I. Menolfi , Martin Leo Schmatz , Thomas H. Toifl
发明人： Christian I. Menolfi , Martin Leo Schmatz , Thomas H. Toifl
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/06 , H04L7/033 , H04L7/0337
摘要： A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.
摘要翻译：用于产生多相的信号发生器包括具有至少一个第一可调节延迟级的环形振荡器和串行布置的至少一个第二延迟级，其中第一延迟级的输出被提供用于传送至少一个第一输出相位和提供第二延迟级的输出用于传递至少一个第二输出相位和用于调整第一可调延迟级的延迟的调整电路，其中调整电路用于调整第一输出相位与第一输出相位之间的相位关系通过设置第一延迟级的第一传播延迟来实现第二输出相位。

9. 发明授权

US07106104B2 Integrated line driver 失效
标题翻译：集成线路驱动器
公开(公告)号：US07106104B2
公开(公告)日：2006-09-12
申请号：US10977667
申请日：2004-10-29
申请人： Christian I. Menolfi , Thomas H. Toifl , Martin L. Schmatz
发明人： Christian I. Menolfi , Thomas H. Toifl , Martin L. Schmatz
IPC分类号： H03K19/175
CPC分类号： H04L25/028 , H03K19/018514 , H04L25/0272 , H04L25/085
摘要： The present invention provides integrated line drivers useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of electrostatic discharge devices and process tolerances are minimized too. An example of an integrated line driver according to the invention comprises a first driver stage followed by a second driver stage, and a feedback unit forming with the second driver stage a control loop. The integrated line drivers are useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of ESD devices and process tolerances are minimized. Advantageously, the integrated line driver according to the invention complies with chip design methodologies, where 10 or more routing metal layers are used.
摘要翻译：本发明提供了可用于驱动具有高数据速率的数据信号的集成线路驱动器，其中线路驱动器的面积消耗被最小化，并且其中静电放电装置的影响和工艺公差也被最小化。根据本发明的集成线路驱动器的示例包括第一驱动器级，之后是第二驱动级，以及与第二驱动级形成控制回路的反馈单元。集成线路驱动器可用于驱动具有高数据速率的数据信号，其中线路驱动器的面积消耗被最小化，并且其中ESD器件和工艺容差的影响最小化。有利地，根据本发明的集成线路驱动器符合使用10个或更多路由选择金属层的芯片设计方法。

10. 发明授权

US08536917B2 Duty cycle adjustment circuit 有权
标题翻译：占空比调节电路
公开(公告)号：US08536917B2
公开(公告)日：2013-09-17
申请号：US13367777
申请日：2012-02-07
申请人： Juergen Hertle , Christian I. Menolfi , Thomas H. Toifl
发明人： Juergen Hertle , Christian I. Menolfi , Thomas H. Toifl
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.
摘要翻译：占空比调整电路包括时钟信号输入节点; 时钟信号输出节点; 耦合到所述时钟信号输入节点的控制电压产生电路; 以及第一反相器，被配置为接收包括在时钟信号输入节点处接收的输入时钟信号和从控制电压产生电路接收的控制电压之和的反相器输入信号，并且在时钟信号输出端输出输出时钟信号节点，其中所述控制电压的变化被配置为改变所述输出时钟信号的占空比。

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