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1. 发明申请

US20060066293A1 Method for testing semiconductor devices and an apparatus therefor 失效
标题翻译：半导体器件的测试方法及其装置
公开(公告)号：US20060066293A1
公开(公告)日：2006-03-30
申请号：US10954920
申请日：2004-09-30
申请人： Ballson Gopal , Ching Teong , Samuel Syn Lim
发明人： Ballson Gopal , Ching Teong , Samuel Syn Lim
IPC分类号： G01R31/28
CPC分类号： G01R31/2867 , G01R1/0408 , G01R31/2849
摘要： A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.
摘要翻译：公开了一种用于测试集成电路装置并将这些装置加载到测试板中用于进一步测试的方法及其装置。该方法允许在两种操作模式之间进行选择。在第一模式中，集成电路器件在放入测试板之前进行电气测试以便进一步测试。在第二模式中，集成电路器件被放置在测试板中后进行测试。该装置允许在第一模式和第二模式之间进行选择。在任一模式下，测试板上的测试设备和插座的信息都用于智能地加载测试板。智能加载意味着被测设备（DUT）不被放置在不良插槽中，测试不良的设备将从测试板上移除，并且可以选择在测试之前对DUT进行环境测试之前，将另一个DUT替换为失败的DUT 董事会进行了。

2. 发明申请

US20070040570A1 Method for testing semiconductor devices and an apparatus therefor 审中-公开
标题翻译：半导体器件的测试方法及其装置
公开(公告)号：US20070040570A1
公开(公告)日：2007-02-22
申请号：US11589389
申请日：2006-10-30
申请人： Ballson Gopal , Ching Teong , Samuel Lim
发明人： Ballson Gopal , Ching Teong , Samuel Lim
IPC分类号： G01R31/26
CPC分类号： G01R31/2867 , G01R1/0408 , G01R31/2849
摘要： A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.
摘要翻译：公开了一种用于测试集成电路装置并将这些装置加载到测试板中用于进一步测试的方法及其装置。该方法允许在两种操作模式之间进行选择。在第一模式中，集成电路器件在放入测试板之前进行电气测试以便进一步测试。在第二模式中，集成电路器件被放置在测试板中后进行测试。该装置允许在第一模式和第二模式之间进行选择。在任一模式下，测试板上的测试设备和插座的信息都用于智能地加载测试板。智能加载意味着被测设备（DUT）不被放置在不良插槽中，测试不良的设备将从测试板上移除，并且可以选择在测试之前对DUT进行环境测试之前，将另一个DUT替换为失败的DUT 董事会进行了。

3. 发明申请

US20070040569A1 Method for testing semiconductor devices and an apparatus therefor 审中-公开
公开(公告)号：US20070040569A1
公开(公告)日：2007-02-22
申请号：US11589331
申请日：2006-10-30
申请人： Ballson Gopal , Ching Teong , Samuel Lim
发明人： Ballson Gopal , Ching Teong , Samuel Lim
IPC分类号： G01R31/26
CPC分类号： G01R31/2867 , G01R1/0408 , G01R31/2849
摘要： A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.

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