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1. 发明授权

US08258815B2 Clock generator circuits for generating clock signals 有权
标题翻译：用于产生时钟信号的时钟发生器电路
公开(公告)号：US08258815B2
公开(公告)日：2012-09-04
申请号：US12716912
申请日：2010-03-03
申请人： Chia Ching Li , Hsin Yi Ho , Chun Hsiung Hung
发明人： Chia Ching Li , Hsin Yi Ho , Chun Hsiung Hung
IPC分类号： H03K19/096 , H03K5/01
CPC分类号： H03K19/096
摘要： The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V1, a first current generator to generate a first mirror current during a first half cycle based on the reference current, a first capacitor including a first end, and a first transistor having a first threshold voltage VTH1. The first transistor includes a gate to receive the first voltage V1, a drain coupled to the first current generator and a source coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle, wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.
摘要翻译：本发明涉及一种用于产生时钟信号的电路。该电路包括用于产生参考电流并提供第一电压V1的电流源，第一电流发生器，用于在基于参考电流的第一半周期期间产生第一反射镜电流，第一电容器，包括第一端和第一电压晶体管具有第一阈值电压VTH1。第一晶体管包括接收第一电压V1的栅极，耦合到第一电流发生器的漏极和耦合到第一电容器的第一端的源，以便允许第一反射镜电流在第一半期间对第一电容器充电循环，其中所述前半周期的周期是所述第一偏置电压V1减去所述第一阈值电压VTH1的函数。

2. 发明申请

US20110058414A1 MEMORY WITH MULTIPLE REFERENCE CELLS 有权
标题翻译：具有多个参考电池的存储器
公开(公告)号：US20110058414A1
公开(公告)日：2011-03-10
申请号：US12555872
申请日：2009-09-09
申请人： Hsin-Yi Ho , Chia-Ching Li
发明人： Hsin-Yi Ho , Chia-Ching Li
IPC分类号： G11C16/04 , G11C16/06 , G11C7/02
CPC分类号： G11C7/04 , G11C11/56 , G11C11/5642 , G11C2211/5634
摘要： A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.
摘要翻译：存储器包括存储器阵列，读出放大器和参考电路。存储器阵列包括存储器单元。读出放大器包括耦合到存储单元的第一端子和第二端子。参考电路包括第一参考单元，第二参考单元和开关。第一参考单元具有用于基于第一参考字线电压提供第一参考电流的第一参考阈值电压。第二参考单元具有第二参考阈值电压，用于基于第二参考字线电压提供第二参考电流。响应于控制信号，开关选择性地将第一和第二参考电流中的一个提供给第二端子。第一和第二参考字线电压对应于不同的电压电平。

3. 发明授权

US08077513B2 Method and apparatus for programming a multi-level memory 有权
标题翻译：用于编程多级存储器的方法和装置
公开(公告)号：US08077513B2
公开(公告)日：2011-12-13
申请号：US12566144
申请日：2009-09-24
申请人： Hsin-Yi Ho , Chia-Ching Li , Chun-Hsiung Hung
发明人： Hsin-Yi Ho , Chia-Ching Li , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/3436
摘要： A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV1′), programming the first memory cell targeted to the first level in the first program phase, and verifying the first memory cell with a first post program-verify voltage of the first program phase (PV1′) in which the first post program-verify voltage is different from the first preliminary voltage. A corresponding apparatus is also provided.
摘要翻译：编程包括多个存储器单元的存储器件的方法可以包括使用第一编程相位（PPV1'）的第一初级电压来验证目标为第一电平的第一存储器单元，编程针对第一级的第一存储器单元在第一编程阶段中，并且以第一编程后验证电压与第一初步电压不同的第一编程相位（PV1'）的第一后编程验证电压来验证第一存储单元。还提供了相应的装置。

4. 发明申请

US20110215837A1 CLOCK GENERATOR CIRCUITS FOR GENERATING CLOCK SIGNALS 有权
标题翻译：用于产生时钟信号的时钟发生器电路
公开(公告)号：US20110215837A1
公开(公告)日：2011-09-08
申请号：US12716912
申请日：2010-03-03
申请人： Chia Ching LI , Hsin Yi HO , Chun Hsiung HUNG
发明人： Chia Ching LI , Hsin Yi HO , Chun Hsiung HUNG
IPC分类号： H03K19/096
CPC分类号： H03K19/096
摘要： The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V1, a first current generator to generate a first mirror current during a first half cycle based on the reference current, a first capacitor including a first end, and a first transistor having a first threshold voltage VTH1. The first transistor includes a gate to receive the first voltage V1, a drain coupled to the first current generator and a source coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle, wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.
摘要翻译：本发明涉及一种用于产生时钟信号的电路。该电路包括用于产生参考电流并提供第一电压V1的电流源，第一电流发生器，用于在基于参考电流的第一半周期期间产生第一反射镜电流，第一电容器，包括第一端和第一电压晶体管具有第一阈值电压VTH1。第一晶体管包括接收第一电压V1的栅极，耦合到第一电流发生器的漏极和耦合到第一电容器的第一端的源，以便允许第一反射镜电流在第一半期间对第一电容器充电循环，其中所述前半周期的周期是所述第一偏置电压V1减去所述第一阈值电压VTH1的函数。

5. 发明申请

US20110069544A1 METHOD AND APPARATUS FOR PROGRAMMING A MULTI-LEVEL MEMORY 有权
标题翻译：用于编程多级存储器的方法和装置
公开(公告)号：US20110069544A1
公开(公告)日：2011-03-24
申请号：US12566144
申请日：2009-09-24
申请人： Hsin-Yi Ho , Chia-Ching Li , Chun-Hsiung Hung
发明人： Hsin-Yi Ho , Chia-Ching Li , Chun-Hsiung Hung
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/3436
摘要： A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV1′), programming the first memory cell targeted to the first level in the first program phase, and verifying the first memory cell with a first post program-verify voltage of the first program phase (PV1′) in which the first post program-verify voltage is different from the first preliminary voltage. A corresponding apparatus is also provided.
摘要翻译：编程包括多个存储器单元的存储器件的方法可以包括使用第一编程相位（PPV1'）的第一初级电压来验证目标为第一电平的第一存储器单元，编程针对第一级的第一存储器单元在第一编程阶段中，并且以第一编程后验证电压与第一初步电压不同的第一编程相位（PV1'）的第一后编程验证电压来验证第一存储单元。还提供了相应的装置。

6. 发明授权

US08189357B2 Memory with multiple reference cells 有权
标题翻译：具有多个参考单元的内存
公开(公告)号：US08189357B2
公开(公告)日：2012-05-29
申请号：US12555872
申请日：2009-09-09
申请人： Hsin-Yi Ho , Chia-Ching Li
发明人： Hsin-Yi Ho , Chia-Ching Li
IPC分类号： G11C11/34
CPC分类号： G11C7/04 , G11C11/56 , G11C11/5642 , G11C2211/5634
摘要： A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.
摘要翻译：存储器包括存储器阵列，读出放大器和参考电路。存储器阵列包括存储器单元。读出放大器包括耦合到存储单元的第一端子和第二端子。参考电路包括第一参考单元，第二参考单元和开关。第一参考单元具有用于基于第一参考字线电压提供第一参考电流的第一参考阈值电压。第二参考单元具有第二参考阈值电压，用于基于第二参考字线电压提供第二参考电流。响应于控制信号，开关选择性地将第一和第二参考电流中的一个提供给第二端子。第一和第二参考字线电压对应于不同的电压电平。

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