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1. 发明授权

US08558295B2 Nonvolatile memory cell and method of manufacturing the same 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US08558295B2
公开(公告)日：2013-10-15
申请号：US12838878
申请日：2010-07-19
申请人： Sung Min Yoon , Chun Won Byun , Shin Hyuk Yang , Sang Hee Park , Soon Won Jung , Seung Youl Kang , Chi Sun Hwang , Byoung Gon Yu
发明人： Sung Min Yoon , Chun Won Byun , Shin Hyuk Yang , Sang Hee Park , Soon Won Jung , Seung Youl Kang , Chi Sun Hwang , Byoung Gon Yu
IPC分类号： H01G7/06
CPC分类号： H01L29/6684 , B82Y10/00 , G11C11/22 , H01L21/28291 , H01L27/1159 , H01L29/78391
摘要： Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.
摘要翻译：提供一种非易失性存储单元及其制造方法。非易失性存储单元包括存储晶体管和驱动晶体管。存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。存储晶体管和驱动晶体管设置在同一衬底上。非易失性存储单元在可见光区域是透明的。

2. 发明授权

US08476106B2 Transparent nonvolatile memory thin film transistor and method of manufacturing the same 有权
标题翻译：透明非易失性存储器薄膜晶体管及其制造方法
公开(公告)号：US08476106B2
公开(公告)日：2013-07-02
申请号：US13469558
申请日：2012-05-11
申请人： Sung Min Yoon , Shin Hyuk Yang , Soon Won Jung , Seung Youl Kang , Doo Hee Cho , Chun Won Byun , Chi Sun Hwang , Byoung Gon Yu , Kyoung Ik Cho
发明人： Sung Min Yoon , Shin Hyuk Yang , Soon Won Jung , Seung Youl Kang , Doo Hee Cho , Chun Won Byun , Chi Sun Hwang , Byoung Gon Yu , Kyoung Ik Cho
IPC分类号： H01L51/40
CPC分类号： H01L21/28291 , H01L29/78391 , H01L29/7869
摘要： Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process.
摘要翻译：提供了一种透明非易失性存储器薄膜晶体管（TFT）及其制造方法。存储TFT包括设置在透明基板上的源极和漏极。透明半导体薄层设置在源电极和漏电极之间，并且透明基板设置在源极和漏极之间。有机铁电薄层设置在透明半导体薄层上。栅电极与透明半导体薄层对准地设置在有机铁电薄层上。因此，透明非易失性存储器TFT采用有机铁电薄层，氧化物半导体薄层和设置在有机铁电薄层之上和之下的辅助绝缘层，从而能够低成本地制造能够低的透明非易失性存储器件温度过程。

3. 发明申请

US20120315729A1 METHOD OF MANUFACTURING TRANSPARENT TRANSISTOR WITH MULTI-LAYERED STRUCTURES 有权
标题翻译：制造具有多层结构的透明晶体管的方法
公开(公告)号：US20120315729A1
公开(公告)日：2012-12-13
申请号：US13590768
申请日：2012-08-21
申请人： Min Ki RYU , Chi Sun Hwang , Chun Won Byun , Hye Yong Chu , Kyoung Ik Cho
发明人： Min Ki RYU , Chi Sun Hwang , Chun Won Byun , Hye Yong Chu , Kyoung Ik Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/66742 , H01L29/45 , H01L29/4908 , H01L29/786 , H01L29/7869
摘要： A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.
摘要翻译：一种制造透明晶体管的方法，所述透明晶体管包括形成在所述基板上的基板，源极和漏极，每个具有下透明层，金属层和上透明层的多层结构，在所述源极和漏极之间形成的沟道电极和与通道对准的栅电极。下透明层或上透明层由与通道相同的透明半导体层形成。

4. 发明申请

US20120242370A1 INVERTER, NAND GATE, AND NOR GATE 失效
标题翻译：逆变器，NAND门和NOR门
公开(公告)号：US20120242370A1
公开(公告)日：2012-09-27
申请号：US13355479
申请日：2012-01-20
申请人： Sang Hee Park , Chi Sun Hwang , Sung Min Yoon , Him Chan Oh , Kee Chan Park , Tao Ren , Hong Kyun Leem , Min Woo Oh , Ji Sun Kim , Jae Eun Pi , Byeong Hoon Kim , Byoung Gon Yu
发明人： Sang Hee Park , Chi Sun Hwang , Sung Min Yoon , Him Chan Oh , Kee Chan Park , Tao Ren , Hong Kyun Leem , Min Woo Oh , Ji Sun Kim , Jae Eun Pi , Byeong Hoon Kim , Byoung Gon Yu
IPC分类号： H03K19/094
CPC分类号： H03K3/012 , H03K19/094 , H03K19/20
摘要： Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
摘要翻译：公开了一种逆变器，NAND门和NOR门。逆变器包括：上拉单元，由根据施加到栅极的电压向输出端子输出第一电源电压的第二薄膜晶体管构成; 根据施加到门的输入信号，将由接地电压输出到输出端的第五薄膜晶体管构成的下拉单元; 以及根据输入信号将第二电源电压或接地电压施加到第二薄膜晶体管的栅极的上拉驱动器。

5. 发明申请

US20120134197A1 MEMORY CELL AND MEMORY DEVICE USING THE SAME 有权
标题翻译：使用该存储单元的存储单元和存储器件
公开(公告)号：US20120134197A1
公开(公告)日：2012-05-31
申请号：US13300688
申请日：2011-11-21
申请人： Chunwon Byun , ByeongHoon Kim , Sung Min Yoon , Shinhyuk Yang , Min Ki Ryu , Chi-Sun Hwang , Sang-Hee Park , Kyoung Ik Cho
发明人： Chunwon Byun , ByeongHoon Kim , Sung Min Yoon , Shinhyuk Yang , Min Ki Ryu , Chi-Sun Hwang , Sang-Hee Park , Kyoung Ik Cho
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of switching elements are configured to be separately controlled on the basis of the individual control signals so as to prevent each electrode of the ferroelectric transistor from being floated.
摘要翻译：提供一种存储单元，包括：铁电晶体管; 电连接到所述铁电晶体管的多个开关元件; 以及多个控制线，用于将各个控制信号发送到多个开关元件中的每一个，用于分别控制多个开关元件。多个开关元件被配置为基于各个控制信号单独控制，以防止铁电晶体管的每个电极浮动。

6. 发明授权

US08148722B2 Method of manufacturing P-type ZnO semiconductor layer using atomic layer deposition and thin film transistor including the P-type ZnO semiconductor layer 有权
标题翻译：使用原子层沉积制造P型ZnO半导体层的方法和包括P型ZnO半导体层的薄膜晶体管
公开(公告)号：US08148722B2
公开(公告)日：2012-04-03
申请号：US12967538
申请日：2010-12-14
申请人： Sang Hee Park , Chi Sun Hwang , Hye Yong Chu , Jeong Ik Lee
发明人： Sang Hee Park , Chi Sun Hwang , Hye Yong Chu , Jeong Ik Lee
IPC分类号： H01L27/15 , H01L29/26 , H01L29/10 , H01L33/00 , H01L31/12
CPC分类号： H01L29/7869 , C23C16/308 , C23C16/34 , C23C16/407 , C23C16/45529 , C30B25/02 , C30B29/16 , H01L21/02554 , H01L21/02579 , H01L21/0262
摘要： Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.
摘要翻译：提供了使用包含构成薄层的元素的前体和包含p型ZnO半导体层的薄膜晶体管（TFT）之间的表面化学反应来制造透明N掺杂p型ZnO半导体层的方法。该方法包括以下步骤：准备衬底并将衬底装载到腔室中; 将Zn前体和氧前体注入到室中，并且使用原子层沉积（ALD）技术在Zn前体和氧前体之间引起表面化学反应，以在衬底上形成ZnO薄层; 并将Zn前体和氮前体注入到室中，并且使Zn前体和氮前体之间的表面化学反应在ZnO薄层上形成掺杂层。

7. 发明申请

US20110249202A1 POWER REDUCTION TELEVISION WITH PHOTO FRAME 审中-公开
标题翻译：电源减少电视与相框
公开(公告)号：US20110249202A1
公开(公告)日：2011-10-13
申请号：US13080831
申请日：2011-04-06
申请人： Sang Hee PARK , Chi Sun Hwang , Min Ki Ryu
发明人： Sang Hee PARK , Chi Sun Hwang , Min Ki Ryu
IPC分类号： H04N5/66 , H04N3/14
CPC分类号： H04N5/63 , H04N5/64
摘要： A power reduction television with a photo frame is provided. The power reduction television includes a first display configured to display a first video image, a low power second display configured to display a second video image, and a display control unit configured to control the second display to display the second video image, when the first video image is not displayed through the first display.
摘要翻译：提供带有相框的减速电视机。功率降低电视包括被配置为显示第一视频图像的第一显示器，被配置为显示第二视频图像的低功率第二显示器，以及显示控制单元，被配置为当第一视频图像被显示时控制第二显示器显示第二视频图像视频图像不会通过第一个显示屏显示。

8. 发明授权

US08017045B2 Composition for oxide semiconductor thin film and field effect transistor using the composition 有权
标题翻译：使用该组合物的氧化物半导体薄膜和场效应晶体管的组成
公开(公告)号：US08017045B2
公开(公告)日：2011-09-13
申请号：US12331688
申请日：2008-12-10
申请人： Doo Hee Cho , Shin Hyuk Yang , Chun Won Byun , Chi Sun Hwang , Hye Yong Chu , Kyoung Ik Cho
发明人： Doo Hee Cho , Shin Hyuk Yang , Chun Won Byun , Chi Sun Hwang , Hye Yong Chu , Kyoung Ik Cho
IPC分类号： H01B1/02
CPC分类号： H01L29/7869 , H01L29/66969
摘要： Provided is a composition for an oxide semiconductor thin film and a field effect transistor (FET) using the composition. The composition includes from about 50 to about 99 mol % of a zinc oxide (ZnO); from about 0.5 to 49.5 mol % of a tin oxide (SnOx); and remaining molar percentage of an aluminum oxide (AlOx). The thin film formed of the composition remains in amorphous phase at a temperature of 400° C. or less. The FET includes an active layer formed of the composition and has improved electrical characteristics. The FET can be fabricated using a low-temperature process without expensive raw materials, such as In and Ga.
摘要翻译：提供了使用该组合物的氧化物半导体薄膜和场效应晶体管（FET）的组合物。该组合物包含约50-约99mol％的氧化锌（ZnO）; 约0.5〜49.5摩尔％的氧化锡（SnO x）; 和氧化铝（AlOx）的剩余摩尔百分数。由该组合物形成的薄膜在400℃以下的温度下保持为非晶相。 FET包括由该组合物形成的有源层并具有改善的电特性。可以使用低温工艺制造FET，而不需要昂贵的原材料，例如In和Ga。

9. 发明授权

US07952273B2 Organic light emitting diode device 有权
标题翻译：有机发光二极管装置
公开(公告)号：US07952273B2
公开(公告)日：2011-05-31
申请号：US11951149
申请日：2007-12-05
申请人： Lee Mi Do , Kyu Ha Baek , Jeong Ik Lee , Yong Suk Yang , Sung Mook Chung , Hye Yong Chu , Sang Hee Park , Chi Sun Hwang
发明人： Lee Mi Do , Kyu Ha Baek , Jeong Ik Lee , Yong Suk Yang , Sung Mook Chung , Hye Yong Chu , Sang Hee Park , Chi Sun Hwang
IPC分类号： H01J1/62 , H01J63/04
CPC分类号： H01L51/5088 , H01L51/0059 , H01L51/0085 , H01L51/5048 , H01L51/5092
摘要： An organic light emitting diode (OLED) device is provided. The OLED device includes: a substrate; an anode formed on the substrate; a first organic thin layer formed on the anode; an organic emission layer formed on the first organic thin layer; a second organic thin layer formed on the organic emission layer; and a cathode formed on the second organic thin layer, wherein the first and second organic thin layers are formed in a single layer or a multi-layer, and at least a part of the first or second organic thin layer is doped with or formed of an insulator. The OLED device provides excellent durability, long life-time, and increased luminous efficiency by balanced charge injection caused by doping or stacking the insulator into or on the organic thin layer.
摘要翻译：提供了一种有机发光二极管（OLED）装置。 OLED器件包括：衬底; 形成在基板上的阳极; 在阳极上形成的第一有机薄层; 形成在所述第一有机薄层上的有机发光层; 形成在有机发光层上的第二有机薄层; 和形成在所述第二有机薄层上的阴极，其中所述第一和第二有机薄层形成在单层或多层中，并且所述第一或第二有机薄层的至少一部分被掺杂或由绝缘体。 OLED器件通过将绝缘体掺杂或堆叠在有机薄层上或其上而引起的平衡电荷注入，提供优异的耐久性，长的寿命和增加的发光效率。

10. 发明申请

US20100258437A1 APPARATUS FOR REACTIVE SPUTTERING DEPOSITION 审中-公开
标题翻译：反应溅射沉积装置
公开(公告)号：US20100258437A1
公开(公告)日：2010-10-14
申请号：US12741667
申请日：2008-09-02
申请人： Woo Seok Cheong , Chi Sun Hwang , Min Ki Ryu
发明人： Woo Seok Cheong , Chi Sun Hwang , Min Ki Ryu
IPC分类号： C23C14/34
CPC分类号： C23C14/0047 , C23C14/3464
摘要： Provided is a reactive sputtering apparatus, and more particularly, a reactive sputtering apparatus capable of effectively ionizing a reactive gas using inductively coupled plasma (ICP). The reactive sputtering apparatus includes: a chamber having an inlet port for introducing a plasma gas thereinto and an outlet port for exhausting the gas used during reactive sputtering to the exterior; an ICP generator disposed on the chamber, ionizing a reactive gas, and injecting the ionized gas into the chamber; and at least one sputter gun located at a side surface of the chamber and supporting a target. Therefore, the reactive sputtering apparatus can improve an ionization rate of a reactive gas using inductively coupled plasma to reduce a process temperature and improve uniformity and step coverage of thin film deposition at low cost.
摘要翻译：提供了一种反应性溅射装置，更具体地，涉及一种使用电感耦合等离子体（ICP）能够有效地电离反应性气体的反应溅射装置。反应性溅射装置包括：具有用于将等离子体气体引入其中的入口的室和用于将反应性溅射期间使用的气体排出到外部的出口; 设置在所述室上的ICP发生器，使反应气体电离，并将所述电离气体注入所述室中; 以及位于所述室的侧表面处并支撑靶的至少一个溅射枪。因此，反应溅射装置可以使用电感耦合等离子体来提高反应气体的离子化速度，以降低处理温度，并以低成本提高薄膜沉积的均匀性和步骤覆盖。

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