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1. 发明授权

US6151657A Processor with embedded in-circuit programming structures 失效
标题翻译：具有嵌入式在线编程结构的处理器
公开(公告)号：US6151657A
公开(公告)日：2000-11-21
申请号：US952045
申请日：1997-10-03
申请人： Albert C. Sun , Chang-Lun Chen , Chee-Horng Lee
发明人： Albert C. Sun , Chang-Lun Chen , Chee-Horng Lee
IPC分类号： G06F9/445 , G06F12/02
CPC分类号： G06F8/665
摘要： An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself, as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed. The processor and ICP code are responsive to an in-circuit programming update command to write a copy of the in-circuit programming set from a first memory array to a second memory array, and to cause the in-circuit programming to execute the in-circuit programming set from the second memory array to program the non-volatile memory cells of the first memory array with data from the external port.
摘要翻译： PCT No.PCT / US96 / 17302 Sec。 371日期：1997年11月3日 102（e）日期1997年11月3日PCT 1996年10月28日PCT公布。第WO98 / 19234号公报日期1998年5月7日具有在线编程的集成电路的架构允许动态改变在线编程指令集本身以及存储在芯片上的其他软件。该架构基于具有两个或多个嵌入式非易失性存储器阵列组的集成电路中的微控制器，其存储包括在线编程指令集的指令。使用存储在设备上的控制程序，设备与远程伙伴交互地建立在线程序交换，并且在需要时更新包括在线编程指令集的数据和软件。处理器和ICP代码响应于在线编程更新命令，以将在线编程集合的副本从第一存储器阵列写入第二存储器阵列，并且使得在线编程执行在线编程，从第二存储器阵列设置电路编程，以利用来自外部端口的数据对第一存储器阵列的非易失性存储单元进行编程。

2. 发明授权

US5901330A In-circuit programming architecture with ROM and flash memory 失效
标题翻译：具有ROM和闪存的在线编程架构
公开(公告)号：US5901330A
公开(公告)日：1999-05-04
申请号：US818389
申请日：1997-03-13
申请人： Albert C. Sun , Chang-Lun Chen , Chee-Horng Lee
发明人： Albert C. Sun , Chang-Lun Chen , Chee-Horng Lee
IPC分类号： G06F11/00 , G06F9/24 , G06F9/445 , G07F7/10 , G06F12/06 , G06F13/20
CPC分类号： G07F7/1008 , G06F8/65 , G06F9/24 , G06Q20/3552
摘要： An architecture for an integrated circuit with in-circuit programming includes a microcontroller on an integrated circuit and one or more banks of non-volatile memory which store instructions, including an in-circuit programming (ICP) set of instructions. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a device external to the integrated circuit and uses data obtained in the exchange to update software for the microcontroller. Portions of the ICP code which are likely to change between different application environments are stored in reprogrammable flash memory cells. Other portions of the ICP code, which are not likely to change between different application environments, are stored in space-efficient mask ROM memory cells. In this way, the ICP system can be flexibly adapted to different application environments, while conserving on silicon area occupied the ICP system.
摘要翻译：具有在线编程的集成电路的架构包括集成电路上的微控制器和存储指令的一个或多个非易失性存储器组，所述指令包括在线编程（ICP）指令集。使用存储在设备上的控制程序，该设备与集成电路外部的设备交互地建立在线编程交换，并使用交换中获得的数据来更新微控制器的软件。可能在不同应用环境之间变化的ICP代码的部分存储在可重新编程的闪存单元中。在不同的应用环境之间不可能改变的ICP代码的其他部分被存储在节省空间的掩模ROM存储器单元中。这样，ICP系统可以灵活适应不同的应用环境，同时节省了硅面积占用的ICP系统。

3. 再颁专利

USRE45306E1 Image processing method and device thereof 有权
标题翻译：图像处理方法及其装置
公开(公告)号：USRE45306E1
公开(公告)日：2014-12-30
申请号：US13436710
申请日：2012-03-30
申请人： Tsui-Chin Chen , Dze-Chang Wang , Hsiao-Ming Huang , Chang-Lun Chen , Ho-lin Wang , Chui-Hsun Chiu
发明人： Tsui-Chin Chen , Dze-Chang Wang , Hsiao-Ming Huang , Chang-Lun Chen , Ho-lin Wang , Chui-Hsun Chiu
IPC分类号： H04N5/14 , H04N5/253
CPC分类号： H04N7/0112 , H04N5/44 , H04N5/445 , H04N21/44008 , H04N21/4884
摘要： An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.
摘要翻译：提供了一种图像处理方法及其装置。该设备包括捕获设备和处理器。捕获装置用于接收多个帧，并且比较至少两个相邻帧以根据其间的差分值获得区域选择信号。处理器连接到捕获装置，用于接收区域选择信号，并将每个相邻帧分成至少两个区域。相邻帧的每个区域分别通过图像处理步骤执行，然后将这些区域的图像组合以获得结果帧。

4. 发明申请

US20060244823A1 IMAGE PROCESSING METHOD AND DEVICE THEREOF 有权
标题翻译：图像处理方法及其装置
公开(公告)号：US20060244823A1
公开(公告)日：2006-11-02
申请号：US11161529
申请日：2005-08-08
申请人： Tsui-Chin Chen , Dze-Chang Wang , Hsiao-Ming Huang , Chang-Lun Chen , Ho-lin Wang , Chui-Hsun Chiu
发明人： Tsui-Chin Chen , Dze-Chang Wang , Hsiao-Ming Huang , Chang-Lun Chen , Ho-lin Wang , Chui-Hsun Chiu
IPC分类号： H04N5/253 , H04N5/14
CPC分类号： H04N7/0112 , H04N5/44 , H04N5/445 , H04N21/44008 , H04N21/4884
摘要： An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.
摘要翻译：提供了一种图像处理方法及其装置。该设备包括捕获设备和处理器。捕获装置用于接收多个帧，并且比较至少两个相邻帧以根据其间的差分值获得区域选择信号。处理器连接到捕获装置，用于接收区域选择信号，并将每个相邻帧分成至少两个区域。相邻帧的每个区域分别通过图像处理步骤执行，然后将这些区域的图像组合以获得结果帧。

5. 发明授权

US07071992B2 Methods and apparatus for bridging different video formats 失效
公开(公告)号：US07071992B2
公开(公告)日：2006-07-04
申请号：US10090176
申请日：2002-03-04
申请人： Chang-Lun Chen , Hsiao-Ming Huang , Meng-Hsiu Wei
发明人： Chang-Lun Chen , Hsiao-Ming Huang , Meng-Hsiu Wei
IPC分类号： H04N7/01
CPC分类号： G09G5/008 , G09G5/391 , H04N7/01 , H04N7/0105
摘要： A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuations in the input and output clock rates, and allows adjustment of the ratio of the input and output the number of lines per frame or number of pixels per line so that output device specifications are not exceeded. A single integrated circuit may provided which is adapted to perform a plurality of techniques, and includes resources by which the user is able to enable and disable such techniques as needed for the particular bridging operation being executed. Bridge logic produces an output video stream which has an output frame rate matching the input frame rate, and in which the output frame has at least one of a variable number of pixels per line within an output frame, and/or a variable number of lines per frame among output frames in a set of more than one output frames.

6. 发明授权

US06842820B2 Processor with embedded in-circuit programming structures 有权
标题翻译：具有嵌入式在线编程结构的处理器
公开(公告)号：US06842820B2
公开(公告)日：2005-01-11
申请号：US10314638
申请日：2002-12-09
申请人： Albert C. Sun , Chang-Lun Chen , Chee-Horng Lee
发明人： Albert C. Sun , Chang-Lun Chen , Chee-Horng Lee
IPC分类号： G06F9/445 , G06F12/00 , G06F9/44
CPC分类号： G06F8/654
摘要： An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself, as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed. The processor and ICP code are responsive to an in-circuit programming update command to write a copy of the in-circuit programming set from a first memory array to a second memory array, and to cause the in-circuit programming to execute the in-circuit programming set from the second memory array to program the non-volatile memory cells of the first memory array with data from the external port.
摘要翻译：具有在线编程的集成电路的架构允许动态地改变在线编程指令集本身以及存储在芯片上的其它软件。该架构基于具有两个或多个嵌入式非易失性存储器阵列组的集成电路中的微控制器，其存储包括在线编程指令集的指令。使用存储在设备上的控制程序，设备与远程伙伴交互地建立在线程序交换，并且在需要时更新包括在线编程指令集的数据和软件。处理器和ICP代码响应于在线编程更新命令，以将在线编程集合的副本从第一存储器阵列写入第二存储器阵列，并且使得在线编程执行在线编程，从第二存储器阵列设置电路编程，以利用来自外部端口的数据对第一存储器阵列的非易失性存储单元进行编程。

7. 发明授权

US06493788B1 Processor with embedded in-circuit programming structures 有权
标题翻译：具有嵌入式在线编程结构的处理器
公开(公告)号：US06493788B1
公开(公告)日：2002-12-10
申请号：US09525835
申请日：2000-03-15
申请人： Albert C. Sun , Chang-Lun Chen , Chee-Horng Lee
发明人： Albert C. Sun , Chang-Lun Chen , Chee-Horng Lee
IPC分类号： G06F1202
CPC分类号： G11C16/102 , G06F8/65
摘要： An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself; as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed. The processor and ICP code are responsive to an in-circuit programming update command to write a copy of the in-circuit programming set from a first memory array to a second memory array, and to cause the in-circuit programming to execute the in-circuit programming set from the second memory array to program the non-volatile memory cells of the first memory array with data from the external port.
摘要翻译：用于具有在线编程的集成电路的架构允许动态地改变在线编程指令集本身; 以及存储在芯片上的其他软件。该架构基于具有两个或多个嵌入式非易失性存储器阵列组的集成电路中的微控制器，其存储包括在线编程指令集的指令。使用存储在设备上的控制程序，设备与远程伙伴交互地建立在线程序交换，并且在需要时更新包括在线编程指令集的数据和软件。处理器和ICP代码响应于在线编程更新命令，以将在线编程集合的副本从第一存储器阵列写入第二存储器阵列，并且使得在线编程执行在线编程，从第二存储器阵列设置电路编程，以利用来自外部端口的数据对第一存储器阵列的非易失性存储单元进行编程。

8. 发明授权

US6167556A System for logic extraction from a layout database 失效
标题翻译：从布局数据库中提取逻辑的系统
公开(公告)号：US6167556A
公开(公告)日：2000-12-26
申请号：US29119
申请日：1998-02-23
申请人： Albert C. Sun , Chee-Horng Lee , Chang-Lun Chen , Chun-hao Li
发明人： Albert C. Sun , Chee-Horng Lee , Chang-Lun Chen , Chun-hao Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and process for logic extraction from the layout of logic blocks is described. Logic design information is extracted from a transistor level net list which is stored in a memory. The transistor level net list in turn is generated from a layout polygon database using techniques in the art. The process comprises processing the transistor level net list in the memory to define groups of transistors according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage and the transistor type. The groups of transistors are analyzed according to their interconnections, and their membership in groups. Finally, logic units are identified in response to the step of analyzing the groups of transistors.
摘要翻译： PCT No.PCT / US97 / 18844 Sec。 371日期1998年2月23日 102（e）日期1998年2月23日PCT 1997年10月14日PCT公布。出版物WO99 / 19818 日期1999年04月22日描述了逻辑块布局逻辑提取的系统和过程。从存储在存储器中的晶体管级网表提取逻辑设计信息。晶体管级网表依次使用本领域的技术从布局多边形数据库生成。该处理包括处理存储器中的晶体管级网表，以根据晶体管级网表中的晶体管是否连接到电源电压来定义晶体管组，晶体管级网表中的晶体管是否连接到参考电压和晶体管类型。晶体管组根据它们的相互关系以及它们的分组成员进行分析。最后，响应于分析晶体管组的步骤来识别逻辑单元。

9. 发明授权

US07688388B2 Image processing method and device thereof 有权
标题翻译：图像处理方法及其装置
公开(公告)号：US07688388B2
公开(公告)日：2010-03-30
申请号：US11161529
申请日：2005-08-08
申请人： Tsui-Chin Chen , Dze-Chang Wang , Hsiao-Ming Huang , Chang-Lun Chen , Ho-lin Wang , Chui-Hsun Chiu
发明人： Tsui-Chin Chen , Dze-Chang Wang , Hsiao-Ming Huang , Chang-Lun Chen , Ho-lin Wang , Chui-Hsun Chiu
IPC分类号： H04N5/14 , H04N5/253
CPC分类号： H04N7/0112 , H04N5/44 , H04N5/445 , H04N21/44008 , H04N21/4884
摘要： An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.
摘要翻译：提供了一种图像处理方法及其装置。该设备包括捕获设备和处理器。捕获装置用于接收多个帧，并且比较至少两个相邻帧以根据其间的差分值获得区域选择信号。处理器连接到捕获装置，用于接收区域选择信号，并将每个相邻帧分成至少两个区域。相邻帧的每个区域分别通过图像处理步骤执行，然后将这些区域的图像组合以获得结果帧。

10. 发明授权

US5623635A Memory consistent pre-ownership method and system for transferring data between and I/O device and a main memory 失效
标题翻译：内存一致的预拥有方法和用于在I / O设备和主存储器之间传输数据的系统
公开(公告)号：US5623635A
公开(公告)日：1997-04-22
申请号：US714888
申请日：1996-09-17
申请人： Chang-Lun Chen , Allen S. C. Wang , Wei-Wen Chang
发明人： Chang-Lun Chen , Allen S. C. Wang , Wei-Wen Chang
IPC分类号： G06F12/08 , G06F12/14 , G06F13/20
CPC分类号： G06F12/0835
摘要： A method and system is disclosed for efficiently transferring a sequence of data words from an I/O device to sequential addresses in a main memory via an I/O bridge. The sequence of data words to be transferred includes one or more subsequences of data words. Each subsequence of data words include only data words destined to addresses of the main memory in which data words of only one data line are stored. The I/O bridge has control logic for receiving a first subsequence of data words corresponding to a currently owned data line and for claiming ownership in one or more of the very next data lines corresponding to the next subsequences of data words to be transferred from the I/O device. The I/O bridge also has a buffer memory for storing a subsequence of the sequence of data words received from the I/O device. The control logic maintains in a pre-own tag array a list of the data lines in which ownership has been successfully claimed and a list in a buffer tag array of storage locations in the buffer memory allocated to receiving data words of particular subsequences of the sequence of data words from the I/O device.
摘要翻译：公开了一种用于通过I / O桥将数据字序列从I / O设备有效传送到主存储器中的顺序地址的方法和系统。要传送的数据字的序列包括数据字的一个或多个子序列。数据字的每个子序列仅包括去往仅存储一条数据线的数据字的主存储器地址的数据字。 I / O桥具有用于接收对应于当前所拥有的数据线的数据字的第一子序列的控制逻辑，并且用于在与要传送的数据字的下一个子序列相对应的下一个数据线中的一个或多个中 I / O设备。 I / O桥还具有用于存储从I / O设备接收的数据字序列的子序列的缓冲存储器。控制逻辑在自己前的标签阵列中保持所有权已被成功声明的数据线的列表以及被分配用于接收该序列的特定子序列的数据字的缓冲存储器中的存储位置的缓冲器标签阵列中的列表来自I / O设备的数据字。

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