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1. 发明授权

US07774739B2 Methods for adjusting shifter width of an alternating phase shifter having variable width 有权
标题翻译：用于调整具有可变宽度的交替移相器的移位器宽度的方法
公开(公告)号：US07774739B2
公开(公告)日：2010-08-10
申请号：US11565215
申请日：2006-11-30
申请人： James Walter Blatchford , Carl Albert Vickery, III
发明人： James Walter Blatchford , Carl Albert Vickery, III
IPC分类号： G06F17/50
CPC分类号： G03F1/30
摘要： In accordance with an embodiment of the invention, there is a method of designing a lithography mask. The method can comprise determining a maximum width of a shifter, wherein the maximum width corresponds to a width of a shifter for a first set of features and determining whether the shifter having the maximum width can be placed in a shifter space for a second set of features. The method can also comprise incrementally decreasing the width of the shifter to be placed into the shifter space for the second set of features when the shifter having the maximum width cannot be placed in the shifter space for a feature in the second set of features until an acceptable shifter width can be determined or until the shifter width is reduced to a predetermined minimum shifter width.
摘要翻译：根据本发明的实施例，存在设计光刻掩模的方法。该方法可以包括确定移位器的最大宽度，其中最大宽度对应于用于第一组特征的移位器的宽度，并且确定具有最大宽度的移位器是否可以被放置在第二组的移位器空间中特征。当具有最大宽度的移位器不能被放置在用于第二组特征中的特征的移位器空间中时，该方法还可以包括递增地减小要放置到用于第二组特征的移位器空间中的移位器的宽度，可以确定可接受的移位器宽度，或者直到移位器宽度减小到预定的最小移位器宽度。

2. 发明授权

US07735056B2 Automated circuit design dimension change responsive to low contrast condition determination in photomask phase pattern 有权
标题翻译：响应于光掩模相位图案中的低对比度条件确定，自动电路设计尺寸变化
公开(公告)号：US07735056B2
公开(公告)日：2010-06-08
申请号：US11392869
申请日：2006-03-30
申请人： Thomas J. Aton , Carl Albert Vickery, III , Shane R. Palmer
发明人： Thomas J. Aton , Carl Albert Vickery, III , Shane R. Palmer
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/70 , G03F1/26
摘要： The present application is directed to methods of forming a phase pattern for an integrated circuit feature described in a design database as having a first target dimension. In one embodiment, the method comprises determining whether forming a phase pattern for the integrated circuit feature described in the design database will result in one or more phase blocks of the same phase type being positioned in relative proximity so as to result in a low contrast condition, selecting a second target dimension that will avoid the low contrast condition if the low contrast condition will result, and forming the phase pattern for an integrated circuit feature having the second target dimension. Systems for forming phase patterns and photomasks comprising the phase patterns of the present application are also disclosed.
摘要翻译：本申请涉及将设计数据库中描述的集成电路特征的相位图形成为具有第一目标尺寸的方法。在一个实施例中，该方法包括确定是否形成设计数据库中描述的集成电路特征的相位图案将导致相同相位类型的一个或多个相位位置相对接近以便导致低对比度条件如果产生低对比度条件，则选择将避免低对比度条件的第二目标尺寸，以及形成具有第二目标尺寸的集成电路特征的相位图案。还公开了用于形成包括本申请的相位图案的相图和光掩模的系统。

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