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1. 发明申请

WO2014138246A1 SYSTEMS AND METHODS FOR DECODING WITH LATE RELIABILITY INFORMATION 审中-公开
标题翻译：用可靠性信息解码的系统和方法
公开(公告)号：WO2014138246A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/020775
申请日：2014-03-05
申请人： MARVELL WORLD TRADE LTD. , NGUYEN, Dung, Viet , CHILAPPAGARI, Shashi, Kiran , NGUYEN, Phong, Sy
发明人： NGUYEN, Dung, Viet , CHILAPPAGARI, Shashi, Kiran , NGUYEN, Phong, Sy
IPC分类号： H04L1/00 , H03M13/11 , H03M13/37 , G06F11/10
CPC分类号： H03M13/1111 , G06F11/1068 , G11C29/00 , H03M13/1105 , H03M13/1108 , H03M13/116 , H03M13/255 , H03M13/2957 , H03M13/37 , H03M13/3707 , H03M13/4138 , H04L1/005 , H04L1/0052 , H04L1/0057
摘要： Systems and methods are provided for decoding data. A variable node value for a variable node is received at a first time, and reliability data for the variable node is received at a second time. The variable node is decoded using a first decoding scheme after the first time and before the second time, and the variable node is decoded using a second decoding scheme different from the first decoding scheme after the second time.
摘要翻译：提供了解码数据的系统和方法。第一次接收到变量节点的变量节点值，并在第二时间接收到可变节点的可靠性数据。在第一时间之后和第二时间之前，使用第一解码方案对变量节点进行解码，并且在第二次之后，使用与第一解码方案不同的第二解码方案对变量节点进行解码。

2. 发明申请

WO2012106255A1 MAPPING DATA TO NON-VOLATILE MEMORY 审中-公开
标题翻译：将数据映射到非易失性存储器
公开(公告)号：WO2012106255A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023165
申请日：2012-01-30
申请人： MARVELL WORLD TRADE LTD. , CHILAPPAGARI, Shashi Kiran , YANG, Xueshi , BURD, Gregory
发明人： CHILAPPAGARI, Shashi Kiran , YANG, Xueshi , BURD, Gregory
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/10 , G11C16/34
摘要： The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure that includes a plurality of multi- level memory cells. The described system includes a controller configured to map a data segment to the plurality of multi -level memory cells. A first portion of a first set of consecutive bits of a data segment (sector 1) is mapped to a first page (LSBpage) associated with the plurality of multi -level memory cells. A second portion of the first set of consecutive bits of the data segment (sectorl) is mapped to a second page (MSB page) associated with the plurality of multi -level memory cells. A first portion of a second set of consecutive bits of the data segment (sector2) is mapped to the first page. A second portion of the second set of consecutive bits of the data segment is mapped to the second page. The first page is associated with bits of a first significance (LSB), and the second page is associated with bits of a second significance (MSB).
摘要翻译：本公开包括与非易失性存储器有关的系统和技术。所描述的系统例如包括包括多个多级存储器单元的非易失性存储器结构。所描述的系统包括被配置为将数据段映射到多个多层存储器单元的控制器。数据段（扇区1）的第一组连续位的第一部分被映射到与多个多层存储器单元相关联的第一页（LSB页）。数据段（扇区1）的第一组连续位的第二部分被映射到与多个多层存储器单元相关联的第二页（MSB页）。数据段（扇区2）的第二组连续位的第一部分被映射到第一页。数据段的第二组连续位的第二部分被映射到第二页。第一页与第一有效位（LSB）的位相关联，并且第二页与第二有效位（MSB）的位相关联。

3. 发明申请

WO2014149738A1 SYSTEMS AND METHODS FOR MULTI-STAGE SOFT INPUT DECODING 审中-公开
标题翻译：用于多级软输入解码的系统和方法
公开(公告)号：WO2014149738A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/020644
申请日：2014-03-05
申请人： MARVELL WORLD TRADE LTD. , CHILAPPAGARI, Shashi, Kiran , BURD, Gregory
发明人： CHILAPPAGARI, Shashi, Kiran , BURD, Gregory
IPC分类号： H04L1/00 , G06F11/10 , H03M13/11 , H03M13/37
CPC分类号： G06F11/1068 , H03M13/1108 , H03M13/1111 , H03M13/1128 , H03M13/3707 , H04L1/0052
摘要： Systems and methods are provided for decoding data. A first decoder attempts to decode the data based on a hard decision input for a symbol. When the attempt to decode the data based on the hard decision input fails, a request is transmitted reliability information for the symbol. Receiving circuitry receives the reliability information for the symbol, and a second decoder decodes the data based on the reliability information.
摘要翻译：提供了解码数据的系统和方法。第一解码器尝试基于用于符号的硬判决输入对数据进行解码。当基于硬判决输入解码数据的尝试失败时，发送请求被发送用于符号的可靠性信息。接收电路接收符号的可靠性信息，第二解码器基于可靠性信息对数据进行解码。

4. 发明申请

WO2014126750A1 BIT FLIPPING DECODING WITH RELIABILITY INPUTS FOR LDPC CODES 审中-公开
标题翻译：用于LDPC码的可靠性输入的位移解码
公开(公告)号：WO2014126750A1
公开(公告)日：2014-08-21
申请号：PCT/US2014/014697
申请日：2014-02-04
申请人： MARVELL WORLD TRADE LTD. , VARNICA, Nedeljko , NGUYEN, Dung, Viet , CHILAPPAGARI, Shashi, Kiran
发明人： VARNICA, Nedeljko , NGUYEN, Dung, Viet , CHILAPPAGARI, Shashi, Kiran
IPC分类号： H03M13/11 , H03M13/45
CPC分类号： H03M13/1108 , H03M13/1137 , H03M13/1171
摘要： Systems and methods are provided for bit flipping decoding with reliability inputs for LDPC codes. An LDPC decoder receives a variable node value and reliability data for a variable node, and check node values for check nodes associated with the variable node. Circuitry generates an updated variable node value, based on the received reliability data and the received check node values. The circuitry also generates, for at least one check node, an updated check node value based on the updated variable node value. An update rule may be based on whether checks of the variable node value are satisfied or unsatisfied, whether the variable node value has been previously updated, flipped, or toggled, based on the value of the reliability data, or a suitable combination thereof.
摘要翻译：提供了用于LDPC码的可靠性输入的位翻转解码的系统和方法。 LDPC解码器接收变量节点的可变节点值和可靠性数据，并且检查与变量节点相关联的校验节点的节点值。电路根据接收的可靠性数据和接收到的校验节点值产生更新的变量节点值。对于至少一个校验节点，电路还基于更新的变量节点值生成更新的校验节点值。更新规则可以基于是否满足或不满足变量节点值的检查，基于可靠性数据的值或其适当的组合，变量节点值是否已经被先前更新，翻转或切换。

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