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1. 发明申请

US20100197109A1 METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件隔离结构的方法
公开(公告)号：US20100197109A1
公开(公告)日：2010-08-05
申请号：US12639035
申请日：2009-12-16
申请人： YONG-SIK JEONG , JEONG-UK HAN , WEON-HO PARK , BYUNG-SUP SHIM
发明人： YONG-SIK JEONG , JEONG-UK HAN , WEON-HO PARK , BYUNG-SUP SHIM
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76229
摘要： Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.
摘要翻译：提供了一种形成半导体器件的隔离结构的方法，该半导体器件能够最小化执行图案化处理的次数并具有各种深度的沟槽。该方法包括使用第一图案化工艺部分蚀刻半导体衬底以形成具有第一深度的第一沟槽和第二沟槽。半导体衬底具有第一至第三区域。第一沟槽形成在第一区域中，第二沟槽形成在第二区域中。使用第二图案化工艺部分地蚀刻半导体衬底，使得第三沟槽形成在第三区域中，并且第四沟槽形成在第二区域中。第四个沟槽从第二个沟槽的底部延伸。第三沟槽具有第二深度，第四沟槽具有第三深度。形成了填充第一至第四沟槽的隔离层。

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