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1. 发明申请

US20080036488A1 Fault Tolerant Integrated Circuit Architecture 失效
标题翻译：容错集成电路架构
公开(公告)号：US20080036488A1
公开(公告)日：2008-02-14
申请号：US11766310
申请日：2007-06-21
申请人： Steven Kelem , Jaime Cummins , John Watson , Robert Plunkett , Stephen Wasson , Brian Box , Enno Wein , Charles Furciniti
发明人： Steven Kelem , Jaime Cummins , John Watson , Robert Plunkett , Stephen Wasson , Brian Box , Enno Wein , Charles Furciniti
IPC分类号： H03K19/003
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

2. 发明授权

US07197686B2 Reconfigurable bit-manipulation node 有权
标题翻译：可重配置位操作节点
公开(公告)号：US07197686B2
公开(公告)日：2007-03-27
申请号：US10683563
申请日：2003-10-10
申请人： Brian Box , John M. Rudosky , Walter James Scheuermann
发明人： Brian Box , John M. Rudosky , Walter James Scheuermann
IPC分类号： H03M10/00
CPC分类号： H03M13/3922 , H03M7/40 , H03M13/00 , H03M13/09 , H03M13/15 , H03M13/2792 , H03M13/2957 , H03M13/3905 , H03M13/4107 , H03M13/4161 , H03M13/6508 , H03M13/6511 , H03M13/6513 , H03M13/6516 , H03M13/6519 , H03M13/6569
摘要： A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.
摘要翻译：公开了可重新配置的位操作节点。节点包括被配置为执行多个位向功能的执行单元和被配置为控制执行单元以允许执行面向位功能之一的控制单元。执行单元包括彼此互连以允许执行面向位的功能的多个元件。元件包括可编程蝶形单元，多个不可编程蝶形单元，多个数据路径元件，查找表存储器和重排序存储器。执行单元能够参与多种操作模式之一来执行面向位的功能。操作模式包括可编程模式和多种固定操作模式，包括维特比解码，turbo解码和可变长度编码和解码。数据路径元件包括可编程移位器和可编程组合器。

3. 发明申请

US20050182999A1 Viterbi decoder with survivor bits stored to support look-ahead addressing 有权
标题翻译：具有存储器位的维特比解码器用于支持先行寻址
公开(公告)号：US20050182999A1
公开(公告)日：2005-08-18
申请号：US10784484
申请日：2004-02-18
申请人： John Rudosky , Brian Box , Sharad Sambhwani , Aixin Liu
发明人： John Rudosky , Brian Box , Sharad Sambhwani , Aixin Liu
IPC分类号： H03M13/03 , H03M13/23 , H03M13/41
CPC分类号： H03M13/4169 , H03M13/23
摘要： In accordance with an embodiment of the present invention, a Viterbi decoder is described that operates on convolutional error correcting codes. The decoder allows for a pipelined architecture and a unique partitioning of survivor memory to maintain data integrity. Throughput rate is improved and stalling minimized by accessing memory words using a look-ahead function to fill the pipeline.
摘要翻译：根据本发明的实施例，描述了对卷积纠错码进行操作的维特比解码器。解码器允许流水线架构和幸存者内存的唯一分区，以维护数据完整性。通过使用前瞻功能访问存储器字来填充流水线，提高吞吐率并使其停滞。

4. 发明申请

US20080036493A1 Element Controller for a Resilient Integrated Circuit Architecture 失效
标题翻译：用于弹性集成电路架构的元件控制器
公开(公告)号：US20080036493A1
公开(公告)日：2008-02-14
申请号：US11765986
申请日：2007-06-20
申请人： Steven Kelem , Brian Box
发明人： Steven Kelem , Brian Box
IPC分类号： H03K19/173
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括元件控制器，元件接口和可以由元件类型变化的选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。元件控制器控制电路元件的数据操作的执行。功能分配，路由，故障检测以及重新分配和数据重新路由可以实现多种程序和算法的实时性，为IC提供尽可能在运行过程中出现的缺陷的功能。

5. 发明申请

US20070165453A1 RECONFIGURABLE BIT-MANIPULATION NODE 有权
公开(公告)号：US20070165453A1
公开(公告)日：2007-07-19
申请号：US11682696
申请日：2007-03-06
申请人： Brian Box , John Rudosky , Walter Scheuermann
发明人： Brian Box , John Rudosky , Walter Scheuermann
IPC分类号： G11C11/00
CPC分类号： H03M13/3922 , H03M7/40 , H03M13/00 , H03M13/09 , H03M13/15 , H03M13/2792 , H03M13/2957 , H03M13/3905 , H03M13/4107 , H03M13/4161 , H03M13/6508 , H03M13/6511 , H03M13/6513 , H03M13/6516 , H03M13/6519 , H03M13/6569
摘要： A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

6. 发明授权

US6122335A Method and apparatus for fast burst mode data recovery 有权
标题翻译：用于快速突发模式数据恢复的方法和装置
公开(公告)号：US6122335A
公开(公告)日：2000-09-19
申请号：US410780
申请日：1999-10-01
申请人： Barry D. Colella , Jeffrey A. Masucci , Brian Box , Lewis W. Farrar
发明人： Barry D. Colella , Jeffrey A. Masucci , Brian Box , Lewis W. Farrar
IPC分类号： H04J3/00 , H04L7/02 , H04L7/033 , H04L7/00
CPC分类号： H04L7/0338
摘要： A method of data recovery includes receiving a data stream of data bits and splitting the data stream to N identical input data streams where N is an integer greater than 1. Each of the N input data streams is delayed with respect to the preceding one by a bit time divided by N. Each of the N delayed input data streams is then sampled using a local clock to provide N samples which form an N-bit sample code per clock period. At least two successive sample codes are decoded to select one of the N delayed input data streams most aligned with the local clock. The selected data stream is thereby retimed to the local clock for synchronous processing of the data stream payload. The local system clock is held constant in the presence of multiple asynchronous data streams for improved robustness in overall system performance.
摘要翻译：一种数据恢复方法包括：接收数据比特数据流，并将数据流分解成N个大于1的整数的N个相同的输入数据流.N个输入数据流中的每一个相对于前一个数据流被延迟一个时间除以N.然后使用本地时钟对N个延迟输入数据流中的每一个进行采样，以提供在每个时钟周期形成N比特采样码的N个采样。对至少两个连续的采样码进行解码以选择与本地时钟最对准的N个延迟输入数据流中的一个。因此，所选择的数据流被重新定时到本地时钟，用于数据流有效载荷的同步处理。在存在多个异步数据流的情况下，本地系统时钟保持不变，从而提高整体系统性能的鲁棒性。

7. 发明申请

US20080036489A1 Resilient Integrated Circuit Architecture 失效
标题翻译：弹性集成电路架构
公开(公告)号：US20080036489A1
公开(公告)日：2008-02-14
申请号：US11766297
申请日：2007-06-21
申请人： Steven Kelem , Jaime Cummins , John Watson , Robert Plunkett , Stephen Wasson , Brian Box , Enno Wein , Charles Furciniti
发明人： Steven Kelem , Jaime Cummins , John Watson , Robert Plunkett , Stephen Wasson , Brian Box , Enno Wein , Charles Furciniti
IPC分类号： H03K19/003
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

8. 发明授权

US07331013B2 Viterbi decoder with survivor bits stored to support look-ahead addressing 有权
标题翻译：具有存储器位的维特比解码器用于支持先行寻址
公开(公告)号：US07331013B2
公开(公告)日：2008-02-12
申请号：US10784484
申请日：2004-02-18
申请人： John M. Rudosky , Brian Box , Sharad Sambhwani , Aixin Liu
发明人： John M. Rudosky , Brian Box , Sharad Sambhwani , Aixin Liu
IPC分类号： H03M13/41
CPC分类号： H03M13/4169 , H03M13/23
摘要： In accordance with an embodiment of the present invention, a Viterbi decoder is described that operates on convolutional error correcting codes. The decoder allows for a pipelined architecture and a unique partitioning of survivor memory to maintain data integrity. Throughput rate is improved and stalling minimized by accessing memory words using a look-ahead function to fill the pipeline.
摘要翻译：根据本发明的实施例，描述了对卷积纠错码进行操作的维特比解码器。解码器允许流水线架构和幸存者内存的唯一分区，以维护数据完整性。通过使用前瞻功能访问存储器字来填充流水线，提高吞吐率并使其停滞。

9. 发明授权

US06269137B1 Method and apparatus for fast burst mode data recovery 有权
标题翻译：用于快速突发模式数据恢复的方法和装置
公开(公告)号：US06269137B1
公开(公告)日：2001-07-31
申请号：US09610244
申请日：2000-07-06
申请人： Barry D. Colella , Jeffrey A. Masucci , Brian Box , Lewis W. Farrar
发明人： Barry D. Colella , Jeffrey A. Masucci , Brian Box , Lewis W. Farrar
IPC分类号： H04L700
CPC分类号： H04L7/0338
摘要： A method of data recovery includes receiving a data stream of data bits and splitting the data stream to N identical input data streams where N is an integer greater than 1. Each of the N input data streams is delayed with respect to the preceding one by a bit time divided by N. Each of the N delayed input data streams is then sampled using a local clock to provide N samples which form an N-bit sample code per clock period. At least two successive sample codes are decoded to select one of the N delayed input data streams most aligned with the local clock. The selected data stream is thereby retimed to the local clock for synchronous processing of the data stream payload. The local system clock is held constant in the presence of multiple asynchronous data streams for improved robustness in overall system performance.
摘要翻译：一种数据恢复方法包括：接收数据比特数据流，并将数据流分解成N个大于1的整数的N个相同的输入数据流.N个输入数据流中的每一个相对于前一个数据流被延迟一个时间除以N.然后使用本地时钟对N个延迟输入数据流中的每一个进行采样，以提供在每个时钟周期形成N比特采样码的N个采样。对至少两个连续的采样码进行解码以选择与本地时钟最对准的N个延迟输入数据流中的一个。因此，所选择的数据流被重新定时到本地时钟，用于数据流有效载荷的同步处理。在存在多个异步数据流的情况下，本地系统时钟保持不变，从而提高整体系统性能的鲁棒性。

10. 发明授权

US07873881B2 Reconfigurable bit-manipulation node 有权
标题翻译：可重配置位操作节点
公开(公告)号：US07873881B2
公开(公告)日：2011-01-18
申请号：US11682696
申请日：2007-03-06
申请人： Brian Box , John M. Rudosky , Walter James Scheuermann
发明人： Brian Box , John M. Rudosky , Walter James Scheuermann
IPC分类号： G06F11/00
CPC分类号： H03M13/3922 , H03M7/40 , H03M13/00 , H03M13/09 , H03M13/15 , H03M13/2792 , H03M13/2957 , H03M13/3905 , H03M13/4107 , H03M13/4161 , H03M13/6508 , H03M13/6511 , H03M13/6513 , H03M13/6516 , H03M13/6519 , H03M13/6569
摘要： A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.
摘要翻译：公开了可重新配置的位操作节点。节点包括被配置为执行多个位向功能的执行单元和被配置为控制执行单元以允许执行面向位功能之一的控制单元。执行单元包括彼此互连以允许执行面向位的功能的多个元件。元件包括可编程蝶形单元，多个不可编程蝶形单元，多个数据路径元件，查找表存储器和重排序存储器。执行单元能够参与多种操作模式之一来执行面向位的功能。操作模式包括可编程模式和多种固定操作模式，包括维特比解码，turbo解码和可变长度编码和解码。数据路径元件包括可编程移位器和可编程组合器。

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