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1. 发明授权

US06410434B1 Method and apparatus for formation of in-situ doped amorphous semiconductor film 有权
标题翻译：用于形成原位掺杂的非晶半导体膜的方法和装置
公开(公告)号：US06410434B1
公开(公告)日：2002-06-25
申请号：US09521591
申请日：2000-03-09
申请人： Balaraman Mani
发明人： Balaraman Mani
IPC分类号： H01L2144
CPC分类号： C23C16/4401 , C23C16/24 , C23C16/4581 , H01L21/28035 , H01L21/28525 , H01L21/28556 , H01L21/32055 , Y10S118/90
摘要： A LPCVD (Low Pressure Chemical Vapor Deposition) process is used for formation of a doped amorphous semiconductor film with in-situ doping of the semiconductor film on a plurality of semiconductor wafers with reduced defects and with predictable electrical characteristics. The plurality of semiconductor wafers are placed in a reaction chamber. The pressure within the reaction chamber is set to be less than approximately 1.0 Torr, and the temperature within the reaction chamber is set to a predetermined temperature in a range of from about 500° Celsius to about 550° Celsius. A semiconductor film reactant and a dopant reactant are introduced into the reaction chamber through at least two gas inlets. Each gas inlet is disposed on a respective location of the reaction chamber near the pluralty of semiconductor wafers, and each gas inlet carries both of the semiconductor film reactant and the dopant reactant. The doped amorphous semiconductor film is formed from the semiconductor film reactant with in-situ doping from the dopant reactant on the plurality of semiconductor wafers in a LPCVD (Low Pressure Chemical Vapor Deposition) process. With the at least two gas inlets carrying the semiconductor film reactant and the dopant reactant in the LPCVD (Low Pressure Chemical Vapor Deposition) process, the doped amorphous semiconductor film deposited on the plurality of semiconductor wafers has more predictable and uniform electrical characteristics such as sheet resistance across a semiconductor wafer.
摘要翻译：使用LPCVD（低压化学气相沉积）工艺来形成掺杂的非晶半导体膜，其具有在具有减少的缺陷并且具有可预测的电特性的多个半导体晶片上原位掺杂半导体膜。将多个半导体晶片放置在反应室中。反应室内的压力设定为小于约1.0Torr，并且将反应室内的温度设定在约500摄氏度至约550摄氏度范围内的预定温度。半导体膜反应物和掺杂剂反应物通过至少两个气体入口引入反应室。每个气体入口设置在靠近多个半导体晶片的反应室的相应位置上，并且每个气体入口承载半导体膜反应物和掺杂剂反应物两者。掺杂的非晶半导体膜由LPCVD（低压化学气相沉积）工艺中的多个半导体晶片上的掺杂剂反应物原位掺杂的半导体膜反应物形成。在LPCVD（低压化学气相沉积）工艺中，至少两个气体入口携带半导体膜反应物和掺杂剂反应物，沉积在多个半导体晶片上的掺杂非晶半导体膜具有更可预测和均匀的电特性，例如片跨半导体晶片的电阻。

2. 发明授权

US06536370B2 Elapsed time indicator for controlled environments and method of use 失效
标题翻译：受控环境的经过时间指示器和使用方法
公开(公告)号：US06536370B2
公开(公告)日：2003-03-25
申请号：US09199349
申请日：1998-11-25
申请人： Eric Paton , Balaraman Mani
发明人： Eric Paton , Balaraman Mani
IPC分类号： G01D2100
CPC分类号： G01N31/229 , G01N31/222 , G04F1/00
摘要： Exposure time is determined by a device which is sensitive to an environmental substance in a controlled environment. Embodiments include a humidity sensitive timer treated with a cobalt salt which changes colors after a certain exposure time within the controlled environment. Elapsed time is measured by exposing the timer to a humidity controlled environment and monitoring the timer for a change in color.
摘要翻译：暴露时间由受控环境中对环境物质敏感的装置决定。实施例包括用钴盐处理的湿度敏感的定时器，其在受控环境中的特定曝光时间之后改变颜色。通过将定时器暴露于湿度控制的环境并监测定时器的颜色变化来测量经过的时间。

3. 发明授权

US06448180B2 Deposition of in-situ doped semiconductor film and undoped semiconductor film in the same reaction chamber 失效
标题翻译：在相同的反应室中沉积原位掺杂的半导体膜和未掺杂的半导体膜
公开(公告)号：US06448180B2
公开(公告)日：2002-09-10
申请号：US09776813
申请日：2001-02-05
申请人： Balaraman Mani , Bill Chen
发明人： Balaraman Mani , Bill Chen
IPC分类号： H01L2144
CPC分类号： C23C16/24 , C23C16/4401 , C23C16/4581 , H01L21/28035 , H01L21/28525 , H01L21/28556 , H01L21/32055
摘要： For depositing semiconductor films on a plurality of sets of semiconductor wafers, a first set of semiconductor wafers carried by a wafer boat are placed within a reaction chamber. An in-situ doped amorphous semiconductor film is deposited on the first set of semiconductor wafers while the first set of semiconductor wafers carried by the wafer boat are within the reaction chamber. The first set of semiconductor wafers carried by the wafer boat are removed from the reaction chamber, and the first set of semiconductor wafers are removed from the wafer boat. The wafer boat that is empty of any semiconductor wafers is placed back within the reaction chamber. A first undoped semiconductor film having a thickness in a range of from about 8,000 Å (angstroms) to about 12,000 Å (angstroms) is deposited on the wafer boat and on components of the reaction chamber. The wafer boat is then removed from the reaction chamber, and a second set of semiconductor wafers are loaded within the wafer boat. The wafer boat having the second set of semiconductor wafers loaded therein is placed within the reaction chamber. A second undoped semiconductor film is deposited on the second set of semiconductor wafers while the second set of semiconductor wafers carried by the wafer boat are within the reaction chamber. In this manner, the in-situ phosphorous doped amorphous silicon film is deposited on the first set of semiconductor wafers and the undoped polysilicon film is deposited on the second set of semiconductor wafers within the same reaction chamber to minimize cost and labor during integrated circuit manufacture.
摘要翻译：为了在多组半导体晶片上沉积半导体膜，将由晶片舟携带的第一组半导体晶片放置在反应室内。原位掺杂的非晶半导体膜沉积在第一组半导体晶片上，而由晶片舟承载的第一组半导体晶片位于反应室内。将晶片舟携带的第一组半导体晶片从反应室中取出，并将第一组半导体晶片从晶片舟皿中取出。没有任何半导体晶片的晶片舟放回到反应室内。厚度在约8,000埃（埃）至约12,000埃（埃）的第一未掺杂的半导体膜沉积在晶片舟皿和反应室的部件上。然后将晶片舟从反应室中取出，并将第二组半导体晶片装载在晶片舟皿内。将装载有第二组半导体晶片的晶片舟放置在反应室内。第二未掺杂半导体膜沉积在第二组半导体晶片上，而由晶片舟承载的第二组半导体晶片位于反应室内。以这种方式，原位磷掺杂的非晶硅膜沉积在第一组半导体晶片上，并且未掺杂的多晶硅膜沉积在同一反应室内的第二组半导体晶片上，以最小化集成电路制造过程中的成本和劳动。

4. 发明授权

US06452198B1 Minimized contamination of semiconductor wafers within an implantation system 失效
标题翻译：在植入系统内最小化半导体晶片的污染
公开(公告)号：US06452198B1
公开(公告)日：2002-09-17
申请号：US09893847
申请日：2001-06-28
申请人： Balaraman Mani , Bill Chen , Che-Hoo Ng
发明人： Balaraman Mani , Bill Chen , Che-Hoo Ng
IPC分类号： H01J3720
CPC分类号： H01J37/3171
摘要： Contamination of semiconductor wafers are minimized during implantation processes within an implantation system. An implantation chamber of the implantation system and components within the implantation chamber are coated with additional material to minimize contaminants within the implantation chamber. For example, surfaces of the implantation chamber and/or the components of the implantation chamber are coated by performing an implantation process with a coating dopant before a semiconductor wafer is placed within the implantation chamber. In this manner, contaminants on the surfaces of the implantation chamber and/or the components within the implantation chamber are substantially coated and encapsulated with the coating dopant to prevent contact of the contaminant with the semiconductor wafer placed within the implantation chamber. Alternatively, shields are placed on surfaces of the implantation chamber and/or on surfaces of the components of the implantation chamber during an implantation process for a first semiconductor wafer having a contaminant source. Such shields are amenable for absorbing the contaminant and are removed after this implantation process and before a second semiconductor wafer is placed within the implantation chamber to minimize contamination of the second semiconductor wafer.
摘要翻译：在植入系统内的植入过程期间，半导体晶片的污染被最小化。植入系统的植入室和植入室内的组件涂覆有额外的材料以最小化植入室内的污染物。例如，在将半导体晶片放置在植入室内之前，通过执行具有涂层掺杂剂的注入工艺来涂覆注入室的表面和/或注入室的部件。以这种方式，植入室表面上的污染物和/或植入室内的组分被涂覆掺杂剂基本上涂覆和封装，以防止污染物与放置在植入室内的半导体晶片的接触。或者，在具有污染源的第一半导体晶片的注入过程期间，将屏蔽物放置在注入室的表面和/或植入室的部件的表面上。这种屏蔽件适于吸收污染物并且在该注入工艺之后并且在将第二半导体晶片放置在注入室内之前被去除以最小化第二半导体晶片的污染。

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