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1. 发明申请

WO2013014547A1 Tunnel field-effect transistor 审中-公开
标题翻译：隧道场效应晶体管
公开(公告)号：WO2013014547A1
公开(公告)日：2013-01-31
申请号：PCT/IB2012/053088
申请日：2012-06-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , MOSELUND, Kirsten Emilie , STANLEY-MARBELL, Phillip , DOERING, Andreas Christian , BJOERK, Mikael T.
发明人： MOSELUND, Kirsten Emilie , STANLEY-MARBELL, Phillip , DOERING, Andreas Christian , BJOERK, Mikael T.
IPC分类号： H01L29/739 , H01L29/423
CPC分类号： H01L29/7391 , H01L29/42312
摘要： The present invention relates to a tunnel field-effect transistor (1) comprising: at least a source region (2) comprising a corresponding source semiconductor material; at least a drain region (3) comprising a corresponding drain semiconductor material, and at least a channel region (4) comprising a corresponding channel semiconductor material, which is arranged between the source region (2) and the drain region(3), the tunnel field-effect transistor (1)further comprising: at least a source-channel gate electrode (5) provided on at least an interface (5') between the source region (2) and the channel region (4); at least an insulator (5") corresponding to the source-channel gate electrode (5) that is provided between the source-channel gate electrode (5) and at least the interface (5') between the source region (2) and the channel region (4), at least a drain-channel gate electrode (6) provided on at least an interface(6') between the drain region (3) and the channel region(4), and at least an insulator(6") corresponding to the drain-channel gate electrode (6) that is provided between the drain-channel gate electrode (6) and at least the interface (6) between the drain region (3) and the channel region(4).
摘要翻译：隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（1），包括：至少源极区（2），其包括相应的源半导体材料; 至少包括相应的漏极半导体材料的漏极区域（3），以及至少包括布置在源极区域（2）和漏极区域（3）之间的相应沟道半导体材料的沟道区域（4），隧道场效应晶体管（1）还包括：至少设置在源区（2）和沟道区（4）之间的至少界面（5'）上的源沟道栅电极（5）; 至少一个与源极沟道栅电极（5）相对应的绝缘体（5“），该绝缘体设置在源极栅电极（5）和至少源极区（2）和沟道区域（4），至少设置在漏极区域（3）和沟道区域（4）之间的界面（6'）上的漏极 - 沟道栅电极（6），以及至少一个绝缘体（6“ ）设置在漏极沟道栅电极（6）与至少漏极区（3）与沟道区（4）之间的界面（6）之间的漏极沟道栅电极（6）。

2. 发明申请

WO2011151757A1 PRODUCING A MONO-CRYSTALLINE SHEET 审中-公开
标题翻译：生产单晶片
公开(公告)号：WO2011151757A1
公开(公告)日：2011-12-08
申请号：PCT/IB2011/052237
申请日：2011-05-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BJOERK, Mikael T. , RIEL, Heike E. , SCHMID, Heinz
发明人： BJOERK, Mikael T. , RIEL, Heike E. , SCHMID, Heinz
IPC分类号： C30B11/10 , C30B11/12 , C30B13/18 , C30B15/08 , H01L31/18
CPC分类号： C30B15/08 , C30B11/003 , C30B11/02 , C30B11/10 , C30B11/12 , C30B13/18 , C30B15/002 , C30B21/06 , C30B29/06 , C30B29/64 , H01L31/0312 , H01L31/036 , H01L31/1804 , Y02E10/547 , Y02P70/521 , Y10T117/1032
摘要： A method for producing a mono-crystalline sheet (11), in particular a silicon sheet (11), comprises: providing at least two aperture elements (1, 2) forming a gap (3) in-between; providing a molten alloy (4) comprising silicon in the gap (3) between said at least two aperture elements (1, 2); providing a gaseous precursor medium (5) comprising silicon in the vicinity of the molten alloy (4); providing a silicon nucleation crystal (6) in the vicinity of the molten alloy (4); and bringing in contact said silicon nucleation crystal (6) and the molten alloy (4). A device (10, 20) for producing a mono-crystalline sheet (11), in particular a silicon sheet (11), comprises at least two aperture elements (1, 2) at a predetermined distance (D) from each other thereby forming a gap (3), and being adapted to be heated for holding a molten alloy (4) comprising silicon by surface tension in the gap (3) between the aperture elements (1,2 ); a means (15) for supplying a gaseous precursor medium (5) comprising silicon in the vicinity of the molten alloy (4); and a positioning means (16) for holding and moving a nucleation crystal (6) in the vicinity of the molten alloy (2).
摘要翻译：单晶片（11），特别是硅片（11）的制造方法包括：在其间形成间隙（3）的至少两个孔元件（1,2）提供在所述至少两个孔元件（1,2）之间的间隙（3）中包含硅的熔融合金（4）; 在所述熔融合金（4）附近提供包含硅的气态前体介质（5）; 在熔融合金（4）附近提供硅成核晶体（6）; 并与所述硅成核晶体（6）和熔融合金（4）接触。用于制造单晶片（11），特别是硅片（11）的装置（10,20）包括彼此间隔预定距离（D）的至少两个孔元件（1,2），从而形成间隙（3），并且适于被加热以保持在所述孔元件（1,2）之间的所述间隙（3）中通过表面张力保持包含硅的熔融合金（4）; 用于在熔融合金（4）附近供应包含硅的气态前体介质（5）的装置（15）; 以及用于保持和移动熔融合金（2）附近的成核晶体（6）的定位装置（16）。

3. 发明申请

WO2012001600A3 METHOD OF FORMING COMPOUND SEMICONDUCTOR NANOWIRE 审中-公开
标题翻译：形成化合物半导体纳米线的方法
公开(公告)号：WO2012001600A3
公开(公告)日：2012-03-01
申请号：PCT/IB2011052792
申请日：2011-06-24
申请人： IBM , BANGSARUNTIP SARUNYA , BJOERK MIKAEL T , COHEN GUY M , RIEL HEIKE E , SCHMID HEINZ
发明人： BANGSARUNTIP SARUNYA , BJOERK MIKAEL T , COHEN GUY M , RIEL HEIKE E , SCHMID HEINZ
IPC分类号： H01L29/12 , B82Y10/00 , B82Y40/00 , H01L29/06 , H01L29/775 , H01L29/778 , H01L29/78 , H01L33/02
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0243 , H01L21/02521 , H01L21/02543 , H01L21/02603 , H01L21/02658 , H01L29/0673 , H01L29/068 , H01L29/125 , H01L29/42392 , H01L29/775 , H01L29/778 , H01L29/78681 , H01L29/78696
摘要： A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects.
摘要翻译：提供了形成半导体的方法，并且包括将衬垫和纳米线图案化到晶片上，所述纳米线基本上与衬垫侧壁垂直并且基本上平行于晶片表面并且外延生长在纳米线的外表面上，半导体材料，其相对于纳米线的材料而晶格失配并且基本上没有缺陷。

4. 发明申请

WO2012001600A2 METHOD OF FORMING COMPOUND SEMICONDUCTOR 审中-公开
标题翻译：形成化合物半导体的方法
公开(公告)号：WO2012001600A2
公开(公告)日：2012-01-05
申请号：PCT/IB2011/052792
申请日：2011-06-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BANGSARUNTIP, Sarunya , BJOERK, Mikael, T. , COHEN, Guy, M. , RIEL, Heike, E. , SCHMID, Heinz
发明人： BANGSARUNTIP, Sarunya , BJOERK, Mikael, T. , COHEN, Guy, M. , RIEL, Heike, E. , SCHMID, Heinz
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0243 , H01L21/02521 , H01L21/02543 , H01L21/02603 , H01L21/02658 , H01L29/0673 , H01L29/068 , H01L29/125 , H01L29/42392 , H01L29/775 , H01L29/778 , H01L29/78681 , H01L29/78696
摘要： A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects.
摘要翻译：提供了形成半导体的方法，并且包括将衬垫和纳米线图案化到晶片上，所述纳米线基本上与衬垫侧壁垂直并且基本上平行于晶片表面并且外延生长在纳米线的外表面上，半导体材料，其相对于纳米线的材料而晶格失配并且基本上没有缺陷。

5. 发明申请

WO2011051854A1 SEMICONDUCTOR DEVICES WITH SCREENING COATING TO INHIBIT DOPANT DEACTIVATION 审中-公开
标题翻译：具有屏蔽涂层的半导体器件，以抑制眩光消除
公开(公告)号：WO2011051854A1
公开(公告)日：2011-05-05
申请号：PCT/IB2010/054707
申请日：2010-10-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BJOERK, Mikael, T. , KNOCH, Joachim , RIEL, Heike, E. , RIESS, Walter, Heinrich , SCHMID, Heinz
发明人： BJOERK, Mikael, T. , KNOCH, Joachim , RIEL, Heike, E. , RIESS, Walter, Heinrich , SCHMID, Heinz
IPC分类号： H01L29/775 , H01L23/31 , H01L23/29 , H01L29/40
CPC分类号： H01L29/775 , B82Y10/00 , H01L23/29 , H01L29/0665 , H01L29/402 , H01L29/42392 , H01L29/78606 , H01L29/78621 , H01L29/78696 , H01L2924/0002 , Y10S977/773 , Y10S977/78 , H01L2924/00
摘要： Semiconductor devices (10, 15, 17, 19) having gate- source/drain extension regions (6, 7) are provided together with methods of fabricating such devices. The devices (10, 15, 17, 19) include a doped semiconductor having a source region (2), a drain region (3), a channel (4) between the source and drain regions (2, 3), and extension regions (6, 7) between the channel (4) and each of the source and drain regions (2, 3). A gate (5) is formed on the channel (4), and a screening coating (11, 11a, 11b, 11e) is formed on each extension region (6, 7). The screening coating (11, 11a, 11b, 11e) comprises an insulating layer (12), having a dielectric constant no greater than about half that of the extension region (6, 7), formed directly on the extension regions (6, 7) and a screening layer (13, 13a, 13b, 13c) on the insulating layer (12). The coating is such that the screening layer screens the dopant ionization potential in the extension regions (6, 7) to inhibit dopant deactivation.
摘要翻译：具有栅极 - 源极/漏极延伸区域（6,7）的半导体器件（10,15,17,19）与制造这种器件的方法一起提供。器件（10,15,17,19）包括掺杂半导体，其具有源极区（2），漏极区（3），源区和漏区（2,3）之间的沟道（4）（4）与源极和漏极区域（2,3）中的每一个之间的间隔（6,7）。在通道（4）上形成有栅极（5），并且在每个延伸区域（6,7）上形成有屏蔽层（11,11a，11b，11e）。筛选涂层（11,11a，11b，11e）包括绝缘层（12），其绝缘面积（12）直接形成在扩展区域（6,7）上的介电常数不大于扩展区域（6,7）的大约的一半）和绝缘层（12）上的屏蔽层（13,13a，13b，13c）。涂层使得屏蔽层屏蔽延伸区域（6,7）中的掺杂剂离子化电位以抑制掺杂剂失活。

6. 发明申请

WO2011024152A1 TUNNEL FIELD EFFECT DEVICES 审中-公开
标题翻译：隧道场效应装置
公开(公告)号：WO2011024152A1
公开(公告)日：2011-03-03
申请号：PCT/IB2010/053884
申请日：2010-08-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BJOERK, Mikael T. , KARG, Siegfried F. , KNOCH, Joachim , RIEL, Heike E. , RIESS, Walter H. , SOLOMON, Paul M.
发明人： BJOERK, Mikael T. , KARG, Siegfried F. , KNOCH, Joachim , RIEL, Heike E. , RIESS, Walter H. , SOLOMON, Paul M.
IPC分类号： H01L29/739 , H01L29/06
CPC分类号： H01L29/7391 , B82Y10/00 , H01L29/0665
摘要： An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.
摘要翻译：用于隧道场效应晶体管（TFET）结构的间接感应隧道发射器包括至少部分地围绕细长芯元件的外护套，所述细长芯元件由第一半导体材料形成; 设置在所述外护套和所述芯元件之间的绝缘体层; 所述外护套设置在对应于所述TFET结构的源极区域的位置处; 以及将外护套短路到芯元件的源极接触件; 其中所述外护套被配置为在所述芯部元件的源极区域中引入足够的载流子浓度以在导通状态期间隧穿到所述TFET结构的沟道区域。

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