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1. 发明授权

US08609489B2 Methods of forming memory; and methods of forming vertical structures 有权
标题翻译：形成记忆的方法以及形成垂直结构的方法
公开(公告)号：US08609489B2
公开(公告)日：2013-12-17
申请号：US13154259
申请日：2011-06-06
申请人： David A. Kewley , Brian Cleereman , Stephen W. Russell , Rex Stone , Anthony C. Krauth
发明人： David A. Kewley , Brian Cleereman , Stephen W. Russell , Rex Stone , Anthony C. Krauth
IPC分类号： H01L21/336
CPC分类号： H01L21/32133 , H01L21/0337 , H01L21/28008 , H01L21/28273 , H01L21/28282 , H01L21/32139 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
摘要翻译：一些实施例包括形成存储器的方法。可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。占位符可以通过间隙与所述系列的端部间隔开。可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。可以在第二垂直结构上形成掩模。随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

2. 发明授权

US06835503B2 Use of a planarizing layer to improve multilayer performance in extreme ultra-violet masks 失效
标题翻译：使用平坦化层来改善极端紫外线掩模中的多层性能
公开(公告)号：US06835503B2
公开(公告)日：2004-12-28
申请号：US10122031
申请日：2002-04-12
申请人： Anthony C. Krauth
发明人： Anthony C. Krauth
IPC分类号： G03F900
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , Y10T428/24372
摘要： The present invention relates to fabricating a reticle or mask for use in an extreme ultraviolet (“EUV”) photolithographic process. The EUV reticle comprises a substrate, a planarizing layer formed over a surface of the substrate, and a reflective layer deposited in contact with the planarizing layer. The planarizing layer comprises a material that has superior surface flatness properties and provides a flat surface upon which the reflective layer is deposited. The planarizing layer is spin-coated onto the substrate and comprises a material such as an anti-reflective material, a dielectric material, or a polymer. Since the reflective layer is deposited over the flat surface provided by the planarizing layer, the reflective layer is not compromised by defects in the surface of the substrate.
摘要翻译：本发明涉及制造用于极紫外（“EUV”）光刻工艺的掩模版或掩模。 EUV掩模版包括衬底，在衬底的表面上形成的平坦化层和与平坦化层接触沉积的反射层。平坦化层包括具有优异的表面平整性的材料，并提供沉积有反射层的平坦表面。平坦化层被旋涂在基底上并且包括诸如抗反射材料，介电材料或聚合物的材料。由于反射层沉积在由平坦化层提供的平坦表面上，反射层不会受到基板表面的缺陷的影响。

3. 发明授权

US07972926B2 Methods of forming memory cells; and methods of forming vertical structures 有权
标题翻译：形成记忆细胞的方法以及形成垂直结构的方法
公开(公告)号：US07972926B2
公开(公告)日：2011-07-05
申请号：US12497128
申请日：2009-07-02
申请人： David A. Kewley , Brian Cleereman , Stephen W. Russell , Rex Stone , Anthony C. Krauth
发明人： David A. Kewley , Brian Cleereman , Stephen W. Russell , Rex Stone , Anthony C. Krauth
IPC分类号： H01L21/336
CPC分类号： H01L21/32133 , H01L21/0337 , H01L21/28008 , H01L21/28273 , H01L21/28282 , H01L21/32139 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
摘要翻译：一些实施例包括形成存储器的方法。可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。占位符可以通过间隙与所述系列的端部间隔开。可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。可以在第二垂直结构上形成掩模。随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

4. 发明授权

US07387853B2 Use of a planarizing layer to improve multilayer performance in ultraviolet masks 失效
标题翻译：使用平坦化层来改善紫外线掩模中的多层性能
公开(公告)号：US07387853B2
公开(公告)日：2008-06-17
申请号：US11003806
申请日：2004-12-03
申请人： Anthony C. Krauth
发明人： Anthony C. Krauth
IPC分类号： G03F1/00
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , Y10T428/24372
摘要： The present invention relates to fabricating a reticle or mask for use in an extreme ultraviolet (“EUV”) photolithographic process. The EUV reticle comprises a substrate, a planarizing layer formed over a surface of the substrate, and a reflective layer deposited in contact with the planarizing layer. The planarizing layer comprises a material that has superior surface flatness properties and provides a flat surface upon which the reflective layer is deposited. The planarizing layer is spin-coated onto the substrate and comprises a material such as an anti-reflective material, a dielectric material, or a polymer. Since the reflective layer is deposited over the flat surface provided by the planarizing layer, the reflective layer is not compromised by defects in the surface of the substrate.
摘要翻译：本发明涉及制造用于极紫外（“EUV”）光刻工艺的掩模版或掩模。 EUV掩模版包括衬底，在衬底的表面上形成的平坦化层和与平坦化层接触沉积的反射层。平坦化层包括具有优异的表面平整性的材料，并提供沉积有反射层的平坦表面。平坦化层被旋涂在基底上并且包括诸如抗反射材料，介电材料或聚合物的材料。由于反射层沉积在由平坦化层提供的平坦表面上，反射层不会受到基板表面的缺陷的影响。

5. 发明申请

US20110003469A1 Methods Of Forming Memory Cells; And Methods Of Forming Vertical Structures 有权
标题翻译：形成记忆细胞的方法; 和形成垂直结构的方法
公开(公告)号：US20110003469A1
公开(公告)日：2011-01-06
申请号：US12497128
申请日：2009-07-02
申请人： David A. Kewley , Brian Cleereman , Stephen W. Russell , Rex Stone , Anthony C. Krauth
发明人： David A. Kewley , Brian Cleereman , Stephen W. Russell , Rex Stone , Anthony C. Krauth
IPC分类号： H01L21/28 , H01L21/768
CPC分类号： H01L21/32133 , H01L21/0337 , H01L21/28008 , H01L21/28273 , H01L21/28282 , H01L21/32139 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
摘要翻译：一些实施例包括形成存储器的方法。可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。占位符可以通过间隙与所述系列的端部间隔开。可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。可以在第二垂直结构上形成掩模。随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

6. 发明授权

US06207357B1 Methods of forming photoresist and apparatus for forming photoresist 失效
标题翻译：形成光致抗蚀剂的方法和用于形成光致抗蚀剂的装置
公开(公告)号：US06207357B1
公开(公告)日：2001-03-27
申请号：US09299221
申请日：1999-04-23
申请人： Anthony C. Krauth
发明人： Anthony C. Krauth
IPC分类号： G03C500
CPC分类号： G03F7/162 , G03F7/168
摘要： Methods of forming layers of photoresist and apparatus for forming photoresist are described. In one embodiment, a wafer is provided and photoresist is applied thereover. The wafer is rotated while the photoresist is baked. In another embodiment, a wafer having photoresist formed thereover is positioned at a baking station. After positioning, the wafer is moved while exposed to baking conditions at the station. In another embodiment, a wafer having photoresist applied thereover is positioned on a rotatable hot plate at a photoresist baking station. The rotatable hot plate is rotated during at least some of the time the wafer is baked at the station. In another embodiment, photoresist is applied over a wafer surface and into a predefined non-uniform thickness over the surface. The non-uniform thickness is modified over the surface into a more uniform thickness while the photoresist is baked.
摘要翻译：描述了形成光致抗蚀剂层的方法和用于形成光致抗蚀剂的装置。在一个实施例中，提供晶片并且在其上施加光刻胶。在烘烤光致抗蚀剂的同时旋转晶片。在另一个实施例中，其上形成有光致抗蚀剂的晶片位于烘烤站。在定位之后，晶片在暴露于工位的烘烤条件下移动。在另一个实施例中，其上施加有光致抗蚀剂的晶片位于光致抗蚀剂烘烤站的可旋转热板上。可旋转的热板在至少一些时间在台上烘烤时旋转。在另一个实施例中，光致抗蚀剂被施加在晶片表面上并且在表面上被预定义的不均匀的厚度。不均匀的厚度在表面上被改变成更均匀的厚度，同时烘烤光致抗蚀剂。

7. 发明申请

US20110237081A1 Methods of Forming Memory; and Methods of Forming Vertical Structures 有权
标题翻译：形成记忆的方法和垂直结构形成方法
公开(公告)号：US20110237081A1
公开(公告)日：2011-09-29
申请号：US13154259
申请日：2011-06-06
申请人： David A. Kewley , Brian Cleereman , Stephen W. Russell , Rex Stone , Anthony C. Krauth
发明人： David A. Kewley , Brian Cleereman , Stephen W. Russell , Rex Stone , Anthony C. Krauth
IPC分类号： H01L21/3105
CPC分类号： H01L21/32133 , H01L21/0337 , H01L21/28008 , H01L21/28273 , H01L21/28282 , H01L21/32139 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
摘要翻译：一些实施例包括形成存储器的方法。可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。占位符可以通过间隙与所述系列的端部间隔开。可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。可以在第二垂直结构上形成掩模。随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

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