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1. 发明授权

US08659338B2 Resonant clock distribution network architecture with programmable drivers 有权
标题翻译：具有可编程驱动器的谐振时钟分配网络架构
公开(公告)号：US08659338B2
公开(公告)日：2014-02-25
申请号：US12903154
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： G06F1/04 , H03H11/26
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： A resonant clock distribution network architecture is proposed that uses clock drivers of programmable size and reference clocks of programmable duty cycle to achieve a target clock rise time and clock amplitude with low energy consumption when operating in any one of multiple clock frequencies in resonant or non-resonant mode. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译：提出了一种谐振时钟分配网络架构，其使用可编程大小的时钟驱动器和可编程占空比的参考时钟来实现目标时钟上升时间和具有低能耗的时钟振幅，当在谐振或非谐振时钟的多个时钟频率中工作时，谐振模式。这种网络通常适用于具有各种时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。

2. 发明授权

US08400192B2 Architecture for frequency-scaled operation in resonant clock distribution networks 有权
标题翻译：谐振时钟分配网络中频率规模运算的架构
公开(公告)号：US08400192B2
公开(公告)日：2013-03-19
申请号：US12903168
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： H03B1/00
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： An architecture for resonant clock distribution networks is proposed. This architecture allows for the energy-efficient operation of a resonant clock distribution network at multiple clock frequencies through the deployment of flip-flops that can be selectively enabled. The proposed architecture is primarily targeted at the design of resonant clock networks with integrated inductors and exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
摘要翻译：提出了谐振时钟分配网络的架构。该架构允许通过部署可以选择性地启用的触发器来实现在多个时钟频率下的谐振时钟分配网络的能量效率的操作。所提出的架构主要针对具有集成电感器的谐振时钟网络的设计，并且没有显示电感器开销。这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。此外，它可应用于根据可实现的性能水平对半导体器件进行合并。

3. 发明申请

US20110084775A1 RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE FOR TRACKING PARAMETER VARIATIONS IN CONVENTIONAL CLOCK DISTRIBUTION NETWORKS 有权
标题翻译：用于跟踪常规时钟分配网络中的参数变化的共享时钟分配网络架构
公开(公告)号：US20110084775A1
公开(公告)日：2011-04-14
申请号：US12903188
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： H03B5/12
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译：提出了一种谐振时钟分配网络架构，其使得谐振时钟网络能够跟踪参数变化对传统时钟分配网络的插入延迟的影响，从而限制两个网络之间的时钟偏移并产生增加的性能。这种网络通常适用于具有各种时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。

4. 发明申请

US20110084773A1 ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NETWORKS 有权
标题翻译：谐振时钟分配网络单步执行架构
公开(公告)号：US20110084773A1
公开(公告)日：2011-04-14
申请号：US12903172
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： H03B5/12
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译：提出了一种谐振时钟分配网络架构，其能够通过在谐振时钟驱动器中使用选择性控制和触发器的部署来进行单步操作，其需要时钟在任何两个连续的时间之间保持稳定足够长的时间状态更新。这种网络通常适用于具有各种时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。

5. 发明授权

US06424622B1 Optimal buffer management scheme with dynamic queue length thresholds for ATM switches 失效
标题翻译： ATM交换机动态队列长度阈值的最优缓冲管理方案
公开(公告)号：US06424622B1
公开(公告)日：2002-07-23
申请号：US09249324
申请日：1999-02-12
申请人： Ruixue Fan , Alexander Ishii , Brian Mark , Gopalakrishnan Ramamurthy , Qiang Ren
发明人： Ruixue Fan , Alexander Ishii , Brian Mark , Gopalakrishnan Ramamurthy , Qiang Ren
IPC分类号： H04L1226
CPC分类号： H04L49/3081 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要： A buffer management scheme for an ATM switch where the static and dynamic thresholds are applied appropriately at different levels to ensure efficient and fair usage of buffer memory. A novel dynamic threshold mechanism which, while ensuring fair sharing of memory, maximizes the overall memory utilization. An ATM switch using a dynamic queue threshold scheme, said ATM switch comprising K output port queues and a buffer of B cells sharing said K output port queues, wherein a common threshold is dynamically set for the K output port queues, the common threshold being changed to a new value from an old value when a new cell arrives at any of said K output queues, said new value being a maximum of a length of said any of said K output queues plus one and said old value when total queue length is less than a preset value times B and, said new value being a maximum of a said old value minus one and a statically set minimum buffer threshold when total queue length is greater than or equal to a preset value times B, wherein said preset value is greater than or equal to 0.
摘要翻译：一种用于ATM交换机的缓冲器管理方案，其中静态和动态阈值在不同级别适当地应用以确保缓冲存储器的有效和合理使用。一种新颖的动态阈值机制，在确保公平共享内存的同时，最大限度地提高了内存利用率。一种使用动态队列阈值方案的ATM交换机，所述ATM交换机包括K个输出端口队列和共享所述K个输出端口队列的B个小区的缓冲器，其中为所述K个输出端口队列动态地设置公共阈值，所述公共阈值被改变当新单元到达所述K个输出队列中的任一个时，从旧值到新值，所述新值是所述K个输出队列中的任何一个的长度的最大值加上当总队列长度较少时的所述旧输出队列的长度比预设值乘以B，并且当总队列长度大于或等于预设值乘以B时，所述新值是所述旧值减1的最大值和静态设置的最小缓冲器阈值，其中所述预设值更大大于等于0。

6. 发明授权

US08368450B2 Architecture for adjusting natural frequency in resonant clock distribution networks 有权
标题翻译：谐振时钟分配网络调整固有频率的架构
公开(公告)号：US08368450B2
公开(公告)日：2013-02-05
申请号：US12903166
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： An inductor architecture for resonant clock distribution networks is proposed. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture is primarily targeted at the design of integrated inductors and exhibits relatively low area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
摘要翻译：提出了谐振时钟分配网络的电感结构。该架构允许调整谐振时钟分配网络的固有频率，从而在多个时钟频率下实现能量效率的操作。所提出的架构主要针对集成电感器的设计，并展示相对较低的面积开销。这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。此外，它可应用于根据可实现的性能水平对半导体器件进行合并。

7. 发明授权

US08358163B2 Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks 有权
公开(公告)号：US08358163B2
公开(公告)日：2013-01-22
申请号：US12903188
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

8. 发明申请

US20110140753A1 RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE WITH PROGRAMMABLE DRIVERS 有权
标题翻译：具有可编程驱动程序的共享时钟分配网络架构
公开(公告)号：US20110140753A1
公开(公告)日：2011-06-16
申请号：US12903154
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： H03K3/00
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： A resonant clock distribution network architecture is proposed that uses clock drivers of programmable size and reference clocks of programmable duty cycle to achieve a target clock rise time and clock amplitude with low energy consumption when operating in any one of multiple clock frequencies in resonant or non-resonant mode. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译：提出了一种谐振时钟分配网络架构，其使用可编程大小的时钟驱动器和可编程占空比的参考时钟来实现目标时钟上升时间和具有低能耗的时钟振幅，当在谐振或非谐振时钟的多个时钟频率中工作时，谐振模式。这种网络通常适用于具有各种时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。

9. 发明申请

US20110084774A1 ARCHITECTURE FOR OPERATING RESONANT CLOCK NETWORK IN CONVENTIONAL MODE 有权
标题翻译：在常规模式下操作谐振时钟网络的架构
公开(公告)号：US20110084774A1
公开(公告)日：2011-04-14
申请号：US12903174
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： H03B5/12
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels.
摘要翻译：提出了谐振时钟分配网络的架构。所提出的架构允许在常规模式下谐振时钟分配网络的能量效率操作，使得它满足时钟波形的目标规范。这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。此外，它可应用于根据可实现的性能水平进行半速度测试和二进制分组。

10. 发明申请

US20110084772A1 METHOD FOR SELECTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTION NETWORKS WITH NO INDUCTOR OVERHEAD 有权
标题翻译：在没有电感器的谐振时钟分配网络中选择自然频率的方法
公开(公告)号：US20110084772A1
公开(公告)日：2011-04-14
申请号：US12903163
申请日：2010-10-12
申请人： Marios C. Papaefthymiou , Alexander Ishii
发明人： Marios C. Papaefthymiou , Alexander Ishii
IPC分类号： H03B5/12
CPC分类号： G06F1/04 , G06F1/10 , H03K3/012 , H03K5/00 , H03K5/05 , H03K5/1565
摘要： An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
摘要翻译：描述了谐振时钟分配网络的电感结构。该架构允许调整谐振时钟分配网络的固有频率，从而在多个时钟频率下实现能量效率的操作。所提出的架构没有显示电感开销。这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。此外，它可应用于根据可实现的性能水平对半导体器件进行合并。

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