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1. 发明授权

US08043947B2 Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate 有权
标题翻译：消除在DSB衬底的固相外延期间产生的再结晶边界缺陷的方法
公开(公告)号：US08043947B2
公开(公告)日：2011-10-25
申请号：US11941187
申请日：2007-11-16
申请人： Angelo Pinto , Weize Xiong , Manfred Ramin
发明人： Angelo Pinto , Weize Xiong , Manfred Ramin
IPC分类号： H01L21/425
CPC分类号： H01L21/187 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/76224
摘要： A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.
摘要翻译：一种用于半导体处理的方法提供了具有第一晶体取向，第二晶体取向和设置在第一和第二晶体取向之间的边界区域的DSB半导体本体。边界区域还具有与第一晶体取向和第二晶体取向的界面相关联的缺陷，其中缺陷通常从身体的表面延伸到半导体本体中的距离。从其表面去除半导体本体的牺牲部分，其中去除牺牲部分至少部分地去除缺陷。牺牲部分可以通过在低温下氧化表面来限定，其中氧化至少部分地消耗缺陷。牺牲部分也可以通过CMP去除。在去除牺牲部分之后，可以在缺陷上进一步形成STI特征，其中消耗任何剩余的缺陷。

2. 发明授权

US07897447B2 Use of in-situ HCL etch to eliminate by oxidation recrystallization border defects generated during solid phase epitaxy (SPE) in the fabrication of nano-scale CMOS transistors using direct silicon bond substrate (DSB) and hybrid orientation technology (HOT) 有权
标题翻译：在使用直接硅键合衬底（DSB）和混合取向技术（HOT）的纳米尺度CMOS晶体管的制造中，使用原位HCL蚀刻来消除固相外延（SPE）期间产生的氧化重结晶边界缺陷。
公开(公告)号：US07897447B2
公开(公告)日：2011-03-01
申请号：US12391657
申请日：2009-02-24
申请人： Angelo Pinto
发明人： Angelo Pinto
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , H01L21/02381 , H01L21/02433 , H01L21/02609 , H01L21/02667 , H01L21/823807
摘要： A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an anneal and an exposure to hydrochloric acid. The anneal and acid exposure can be performed within an epitaxial reactor chamber to minimize wafer transport.
摘要翻译：用于减少非晶化，再结晶的切割的晶片层和未变形的切割的晶片层之间的界面处的缺陷的方法可以包括退火和暴露于盐酸。退火和酸暴露可以在外延反应器室内进行以最小化晶片输送。

3. 发明授权

US07855111B2 Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates 有权
标题翻译：混合取向技术（HOT）直接硅键合（DSB）衬底的边界区域缺陷减少
公开(公告)号：US07855111B2
公开(公告)日：2010-12-21
申请号：US12538048
申请日：2009-08-07
申请人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
发明人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
IPC分类号： H01L21/8238 , H01L27/118
CPC分类号： H01L21/26506 , H01L21/187 , H01L21/324 , H01L21/76264 , H01L21/823807 , H01L21/823892 , H01L29/045 , H01L29/665
摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.
摘要翻译：用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。（100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。还公开了用本发明方法形成的集成电路。

4. 发明申请

US20100304547A1 REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDCUTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY 审中-公开
标题翻译：使用DSB基板和热技术在半导体器件制造中的SPE期间减少STI拐角缺陷
公开(公告)号：US20100304547A1
公开(公告)日：2010-12-02
申请号：US12637279
申请日：2009-12-14
申请人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
发明人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
IPC分类号： H01L21/76
CPC分类号： H01L21/76275 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045
摘要： A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
摘要翻译：一种降低混合取向晶体管中的残留STI拐角缺陷的装置和方法，包括：形成直接硅键合衬底，其中具有第二晶体取向的第二硅层以第一晶体取向结合到手柄衬底上，形成衬垫氧化物层在所述第二硅层上，在所述焊盘氧化物层上形成氮化物层，通过所述第二硅层在所述直接硅键合衬底内形成隔离沟槽并进入所述处理衬底，使用光致抗蚀剂构图所述直接硅键合衬底的PMOS区域隔离沟槽的一部分，将直接硅键合衬底的NMOS区域注入和非晶化，去除光致抗蚀剂，进行固相外延，进行再结晶退火，形成STI衬垫，完成前端处理和执行后端处理。

5. 发明申请

US20090057816A1 METHOD TO REDUCE RESIDUAL STI CORNER DEFECTS GENERATED DURING SPE IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DSB SUBSTRATE AND HOT TECHNOLOGY 审中-公开
标题翻译：使用DSB基板和热技术在纳米尺寸CMOS晶体管制造中降低SPE期间产生的残留STI角度缺陷的方法
公开(公告)号：US20090057816A1
公开(公告)日：2009-03-05
申请号：US11847053
申请日：2007-08-29
申请人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
发明人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/76275 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045
摘要： A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
摘要翻译：一种降低混合取向晶体管中的残留STI拐角缺陷的装置和方法，包括：形成直接硅键合衬底，其中具有第二晶体取向的第二硅层以第一晶体取向结合到手柄衬底上，形成衬垫氧化物层在所述第二硅层上，在所述焊盘氧化物层上形成氮化物层，通过所述第二硅层在所述直接硅键合衬底内形成隔离沟槽并进入所述处理衬底，使用光致抗蚀剂构图所述直接硅键合衬底的PMOS区域隔离沟槽的一部分，将直接硅键合衬底的NMOS区域注入和非晶化，去除光致抗蚀剂，进行固相外延，进行再结晶退火，形成STI衬垫，完成前端处理和执行后端处理。

6. 发明授权

US07217322B2 Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer 有权
标题翻译：制造外延硅锗层的方法和包括外延砷原位掺杂硅 - 锗层的集成半导体器件
公开(公告)号：US07217322B2
公开(公告)日：2007-05-15
申请号：US10934188
申请日：2004-09-02
申请人： Jeffrey A. Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
发明人： Jeffrey A. Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
IPC分类号： C30B25/04
CPC分类号： C23C16/42 , C23C16/56 , H01L21/02532 , H01L21/02576
摘要： A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.
摘要翻译：制造用于集成半导体器件的外延硅 - 锗层的方法包括沉积砷原位掺杂硅 - 锗层的步骤，其中砷和锗随后在沉积期间被引入所述硅 - 锗层的不同区域所述硅 - 锗层。通过从锗中分离砷，可避免在沉积过程中砷和锗之间的相互作用，从而允许制造具有可重复掺杂分布的硅 - 锗层。

7. 发明申请

US20060197158A1 Advanced CMOS using Super Steep Retrograde Wells 有权
标题翻译：高级CMOS使用超级陡峭逆行井
公开(公告)号：US20060197158A1
公开(公告)日：2006-09-07
申请号：US11380602
申请日：2006-04-27
申请人： Jeffrey Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory Howard
发明人： Jeffrey Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory Howard
IPC分类号： H01L27/12
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

8. 发明申请

US20050258990A1 On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits 有权
公开(公告)号：US20050258990A1
公开(公告)日：2005-11-24
申请号：US11182981
申请日：2005-07-15
申请人： Jeffrey Babcock , Angelo Pinto , Gregory Howard , Philipp Steinmann , Scott Balster
发明人： Jeffrey Babcock , Angelo Pinto , Gregory Howard , Philipp Steinmann , Scott Balster
IPC分类号： H01L21/02 , H01L21/768 , H01L23/34 , H01L23/525 , H03M1/10
CPC分类号： H01L21/76886 , H01L21/76888 , H01L23/345 , H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.

9. 发明授权

US06646323B2 Zero mask high density metal/insulator/metal capacitor 有权
公开(公告)号：US06646323B2
公开(公告)日：2003-11-11
申请号：US09849730
申请日：2001-05-04
申请人： Christoph Dirnecker , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Angelo Pinto
发明人： Christoph Dirnecker , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Angelo Pinto
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor. The resulting capacitor has a relatively large effective electrode surface area (which is a function of the depth of the via) for a given lateral dimension.

10. 发明授权

US06198154B1 PNP lateral bipolar electronic device 失效
标题翻译： PNP横向双极电子器件
公开(公告)号：US06198154B1
公开(公告)日：2001-03-06
申请号：US09087421
申请日：1998-05-29
申请人： Angelo Pinto , Carlo Alemanni
发明人： Angelo Pinto , Carlo Alemanni
IPC分类号： H01L27082
CPC分类号： H01L29/41708 , H01L27/0823 , H01L29/735
摘要： A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises a semiconductor substrate, doped for conductivity of the P-type, a first buried layer, doped for conductivity of the N-type to provide a base region, and a second layer, overlying the first and having conductivity of the N-type, to provide an active area distinguishable by a P-doped emitter region within the active area being located peripherally and oppositely from a P-doped collector region. The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.
摘要翻译：横向PNP双极电子器件与半导体衬底上的整体集成，以及能够在高频下工作的其他NPN双极器件。 PNP器件结合到电绝缘的多层结构中，该多层结构包括掺杂为P型导电性的半导体衬底，用于提供基极区域的N型导电性掺杂的第一埋层，以及第二层，覆盖第一层并具有N型导电性，以提供由有源区域内的P掺杂发射极区域区分开的有源区域，其位于P掺杂集电极区域周边和相对的位置。横向PNP器件可以在合适的集电极电流值和良好放大的高频下工作，与典型的常规横向PNP器件相比，可提供优异的品质因数。

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