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1. 发明授权

US07583087B2 In-situ monitor of process and device parameters in integrated circuits 有权
标题翻译：现场监控集成电路中的工艺和器件参数
公开(公告)号：US07583087B2
公开(公告)日：2009-09-01
申请号：US11064038
申请日：2005-02-22
申请人： David J. Pilling , Cesar Talledo
发明人： David J. Pilling , Cesar Talledo
IPC分类号： G01R31/08
CPC分类号： G01R31/2882 , G01R31/2853 , G01R31/318541 , G01R31/318555 , G11C29/1201 , G11C29/48
摘要： In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.
摘要翻译：根据本发明，提出了一种形成在集成电路上的测试电路。根据本发明的测试电路包括耦合到参数测试电路的输入电路和耦合到参数测试电路的输出驱动器。参数测试电路的实施例可以包括用于测试集成电路的处理，器件和电路特性的电路。此外，测试电路的一些实施例可以包括在其中包括各种测试电路的序列的扫描路径系统中。此外，可以利用从参数测试电路获得的测试参数来调整集成电路的操作参数。

2. 发明授权

US07692499B2 Digitally compensated highly stable holdover clock generation techniques using adaptive filtering 有权
标题翻译：使用自适应滤波的数字补偿高度稳定的保持时钟生成技术
公开(公告)号：US07692499B2
公开(公告)日：2010-04-06
申请号：US12006368
申请日：2007-12-31
申请人： Xin Liu , Liang Zhang , Yong Wang
发明人： Xin Liu , Liang Zhang , Yong Wang
IPC分类号： H03L7/093 , H03L7/087 , H03L1/00
CPC分类号： H03L7/093 , H03L1/02 , H03L7/099 , H03L7/0996 , H03L7/235
摘要： A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.
摘要翻译：提出了利用集成电路和外部OCXO产生高度稳定的保持时钟的系统和方法。集成电路包括输入参考时钟接收器，相位和频率检测器，其在输入参考时钟信号和反馈时钟信号之间产生误差信号，存储模型参数以预测OCXO的频率变化的数据存储块，适应性滤波模块，其包括数字环路滤波器和用于更新模型参数并且基于该模型预测频率变化的算法，使得系统能够在正常或保持模式下操作的开关，数字控制振荡器和反馈分频器的开关。

3. 发明授权

US07554379B2 High-speed, low-power level shifter for mixed signal-level environments 有权
标题翻译：用于混合信号级环境的高速，低功耗电平转换器
公开(公告)号：US07554379B2
公开(公告)日：2009-06-30
申请号：US11710371
申请日：2007-02-23
申请人： David J. Pilling , Mario Fulam Au
发明人： David J. Pilling , Mario Fulam Au
IPC分类号： H03L5/00
CPC分类号： H03K19/0013 , H03K19/01707 , H03K19/018521
摘要： A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain to gate of any of the transistors. Pull-up transistors are placed in a transition state so that spikes resulting from an increasing or decreasing input voltage turn on or off the pull up transistors to assist in the switching.
摘要翻译：提出了一种允许快速切换同时要求低功耗的电平转换器。根据本发明的一些实施例，电平移位器是双级电平移位电路，其中p沟道和n沟道晶体管被偏置，以便限制任何晶体管的源极到栅极或漏极之间的电势。上拉晶体管处于过渡状态，使得由增加或减小的输入电压引起的尖峰导通或关断上拉晶体管以辅助切换。

4. 发明授权

US07499303B2 Binary and ternary non-volatile CAM 有权
标题翻译：二进制和三元非易失性CAM
公开(公告)号：US07499303B2
公开(公告)日：2009-03-03
申请号：US10950186
申请日：2004-09-24
申请人： Chuen-Der Lien , Shih-Ked Lee
发明人： Chuen-Der Lien , Shih-Ked Lee
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C11/22 , G11C13/0004 , G11C15/02
摘要： A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller coupled to the match line; and a data line controller coupled to the data lines, wherein a write operation is performed by changing a state of the non-volatile storage element by providing data to the at least one data line, wherein a read operation is performed by determining the state of the non-volatile storage element through the at least one data line, and wherein a comparison operation is performed by applying data to the at least one data line and determining a match condition on the match line.
摘要翻译：根据本发明的实施例的CAM单元阵列包括CAM单元的阵列，每个CAM单元包括第一单元，第一单元包括耦合到至少一个第一数据线和匹配线的非易失性存储元件 ; 耦合到匹配线的匹配线控制器; 以及耦合到数据线的数据线控制器，其中通过向所述至少一个数据线提供数据来改变所述非易失性存储元件的状态来执行写入操作，其中通过确定所述非易失性存储元件的状态来执行读取操作所述非易失性存储元件通过所述至少一个数据线，并且其中通过将数据应用于所述至少一条数据线并确定所述匹配线上的匹配条件来执行比较操作。

5. 发明授权

US07474011B2 Method for improved single event latch up resistance in an integrated circuit 有权
标题翻译：在集成电路中改进单事件闭锁电阻的方法
公开(公告)号：US07474011B2
公开(公告)日：2009-01-06
申请号：US11527374
申请日：2006-09-25
申请人： Chuen-Der Lien , Ta-Ke Tien , Pao-Lu Louis Huang
发明人： Chuen-Der Lien , Ta-Ke Tien , Pao-Lu Louis Huang
IPC分类号： H01L27/00 , G06F17/50
CPC分类号： G01R31/2853 , G06F17/5036 , Y10S257/929
摘要： A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.
摘要翻译：一种用于估计集成电路中单事件闩锁发生的过程和系统。该过程包括确定每个连接点与规则形状井中最接近的适当水龙头之间的阻力。发现在不规则形状的井中的每个连接也被识别。最后，该方法可以提出降低集成电路中可能发生单事件闩锁的可能性的建议。

6. 发明授权

US07436224B2 Low variation voltage output differential for differential drivers 有权
公开(公告)号：US07436224B2
公开(公告)日：2008-10-14
申请号：US11494847
申请日：2006-07-27
申请人： Yanbo Wang , Hongquan Wang , Xuexin Ding
发明人： Yanbo Wang , Hongquan Wang , Xuexin Ding
IPC分类号： H03B1/00
CPC分类号： H03K19/00384
摘要： The methods and systems presented herein provide an improved means of correcting the variation of Voltage Output Differential (VOD) in differential drivers. In some embodiments, a high-precision reference voltage is generated not only based on a desired VOD, but also by monitoring the Voltage Common Mode (VCM) in a differential driver. In some embodiments, the VOD is then compared with the high-precision reference voltage to correct the output current. The result is a low-variation output voltage.

7. 发明授权

US07368938B2 Input termination circuitry with high impedance at power off 有权
标题翻译：断电时具有高阻抗的输入终端电路
公开(公告)号：US07368938B2
公开(公告)日：2008-05-06
申请号：US11455074
申请日：2006-06-15
申请人： Xuexin Ding , Hongquan Wang , Weifeng Zhang
发明人： Xuexin Ding , Hongquan Wang , Weifeng Zhang
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005
摘要： An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and the second resistor, and a third transistor having two terminals respectively coupled to the control circuit and a node between the first and the second transistor. The gate of the third transistor is coupled to ground. The gates of the first and the second transistor are coupled to a control circuit that is adapted to provide a control signal to turn the first and the second transistor on or off.
摘要翻译：输入终端电路包括第一和第二电阻器，每个电阻器具有分别耦合到输入终端电路的第一和第二输入端的端子，串联耦合在第一电阻器和第二电阻器之间的第一和第二晶体管，以及具有分别耦合到控制电路的两个端子和第一和第二晶体管之间的节点的第三晶体管。第三晶体管的栅极耦合到地。第一和第二晶体管的栅极耦合到控制电路，该控制电路适于提供控制信号以使第一和第二晶体管接通或断开。

8. 发明授权

US07286438B2 Dual port memory cell with reduced coupling capacitance and small cell size 有权
标题翻译：具有减小的耦合电容和小单元尺寸的双端口存储单元
公开(公告)号：US07286438B2
公开(公告)日：2007-10-23
申请号：US11403370
申请日：2006-04-12
申请人： Chuen-Der Lien , Pao-Lu Louis Huang
发明人： Chuen-Der Lien , Pao-Lu Louis Huang
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/02 , G11C7/1075 , G11C7/18
摘要： A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray and coupling capacitance associated with the bit lines. In one exemplary embodiment, the bit lines from each port that are in closer proximity to the bit lines of the other (or another) port are disposed in different metallization layers to reduce coupling capacitance therebetween. One or more further embodiments can include VSS or VDD line(s) located horizontally between the bit lines and metal to substrate contacts for the bit lines can be formed in opposite corners of the memory device to further reduce capacitance.
摘要翻译：一种双端口或多端口存储器件，包括与第一端口相关联的与第二端口相关联的第二组位线的第一组位线，其中位线布置在不同的金属化层中并且水平分开以减少一个或两个与位线相关的杂散和耦合电容。在一个示例性实施例中，来自更接近另一（或另一）端口的位线的每个端口的位线被布置在不同的金属化层中以减小它们之间的耦合电容。一个或多个另外的实施例可以包括水平位于位线和用于位线的金属到衬底触点之间的V SS或V DD线，可以形成为相反的存储器件的角落，以进一步降低电容。

9. 发明授权

US07110400B2 Random access memory architecture and serial interface with continuous packet handling capability 有权
公开(公告)号：US07110400B2
公开(公告)日：2006-09-19
申请号：US10120648
申请日：2002-04-10
申请人： Stanley Hronik
发明人： Stanley Hronik
IPC分类号： H04L12/28
CPC分类号： H04L49/90
摘要： A random access memory architecture and method of handling data packets is described. According to embodiments of the invention, an apparatus includes a first processing unit for receiving serial data input, a switch, and a plurality of serially connected random access memory devices. The random access memory devices transmit data packets and commands via write input ports, write output ports, read input ports, and read output ports. A method for routing data includes receiving serial data input in a first processing unit, generating a data packet based on the serial data input, transmitting the data packet to a first random access memory device via a write input port, decoding the data packet, determining whether to perform a command in the first random access memory device based on information in the data packet, and transmitting the data packet to a second random access memory device.

10. 发明授权

US06910135B1 Method and apparatus for an intruder detection reporting and response system 有权
标题翻译：入侵者检测报告和响应系统的方法和装置
公开(公告)号：US06910135B1
公开(公告)日：2005-06-21
申请号：US09348377
申请日：1999-07-07
申请人： Steven Phillip Grainger
发明人： Steven Phillip Grainger
IPC分类号： G06F11/00 , G06F21/00 , H04L9/00 , H04L29/06
CPC分类号： H04L63/20 , G06F21/316 , G06F21/552 , H04L63/1416
摘要： A method and apparatus is disclosed for improving the security of computer networks by providing a means operating passively on the network for detecting, reporting and responding to intruders. The system is comprised of a plurality of intruder sensor client computers and associated event correlation engines. Resident in the memory of the client computer and operating in the background is a Tactical Internet Device Protection (TIDP) component consisting of a passive intruder detector and a security Management Information Base (MIB). The passive intruder detector component of the TIDP passively monitors operations performed on the client computer and emits a Simple Network Management Protocol (SNMP) trap to an event correlation engine when it identifies a suspected intruder. The event correlation engine, through the use of a behavior model loaded in its memory, determines whether the user's activities are innocent or those of a perspective intruder. When the event correlation engine is unable to classify a user based on a single trap message, it can request historical information from the security MIB, a database of the operating history of the client computer including a chronology of the illegal operations performed on the client. Once the event correlation engine determines that an intruder is located at an associated client workstation, it generates a status message and transmits the message to all of its subscribers, informing them of the presence and location of a suspected intruder.
摘要翻译：公开了一种用于通过提供在网络上被动地操作以检测，报告和响应入侵者的装置来改善计算机网络的安全性的方法和装置。该系统由多个入侵者传感器客户计算机和相关联的事件相关引擎组成。在客户端计算机的存储器中并在后台运行的是由无源入侵检测器和安全管理信息库（MIB）组成的战术互联网设备保护（TIDP）组件。 TIDP的被动入侵检测器组件被动地监视在客户端计算机上执行的操作，并且当它识别可疑入侵者时，向事件关联引擎发送简单网络管理协议（SNMP）陷阱。事件关联引擎通过使用加载在其内存中的行为模型来确定用户的活动是无辜者还是透视入侵者的活动。当事件关联引擎不能基于单个陷阱消息对用户进行分类时，它可以从安全MIB请求历史信息，该客户端计算机的操作历史的数据库包括在客户机上执行的非法操作的时间顺序。一旦事件相关引擎确定入侵者位于相关联的客户端工作站，则它产生状态消息并将消息发送给所有订户，通知他们怀疑入侵者的存在和位置。

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