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1. 发明公开

US20240006406A1 INTEGRATED CIRCUIT WITH MIXED ROW HEIGHTS 审中-公开
公开(公告)号：US20240006406A1
公开(公告)日：2024-01-04
申请号：US18232759
申请日：2023-08-10
申请人： Taiwan Semiconductor Manufactruing Co., Ltd.
发明人： Kam-Tou SIO , Jiann-Tyng TZENG , Chung-Hsing WANG , Yi-Kan CHENG
IPC分类号： H01L27/02 , H01L27/092
CPC分类号： H01L27/0207 , H01L27/0924 , G06F2111/20
摘要： An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

2. 发明授权

US10727065B2 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US10727065B2
公开(公告)日：2020-07-28
申请号：US16122235
申请日：2018-09-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Chia-Wei Su , Fu-Ting Yen , Ting-Ting Chen , Teng-Chun Tsai
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/02 , H01L29/66 , H01L21/311 , H01L21/285 , H01L21/3105 , H01L21/321 , H01L21/3205 , H01L21/32
摘要： A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.

3. 发明授权

US07608884B2 Scalable split-gate flash memory cell with high source-coupling ratio 有权
标题翻译：具有高源耦合比的可扩展分离式闪存单元
公开(公告)号：US07608884B2
公开(公告)日：2009-10-27
申请号：US11088492
申请日：2005-03-24
申请人： Te-Hsun Hsu , Hung-Cheng Sung
发明人： Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.
摘要翻译：系统和方法提供了闪存中改进的源耦合比。在一个实施例中，具有高源耦合比率的快闪存储器单元系统至少包括具有浮置栅极，漏极和源极的常规浮动栅极器件。浮置栅极形成在第一结上，用于通过从源极到浮置栅极的电子注入来对浮置栅极充电，并且至少第一电介质层叠在浮置栅极的顶部上以形成第二结。至少第一多晶硅层叠在第一电介质的顶部上，第一多晶硅电连接到源极。通过第二结提供到浮栅的电子隧穿对浮置栅极充电，从而增加浮栅的源极耦合比并提高存储电荷的效率。

4. 发明授权

US10693004B2 Via structure with low resistivity and method for forming the same 有权
公开(公告)号：US10693004B2
公开(公告)日：2020-06-23
申请号：US16163970
申请日：2018-10-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kuo-Chiang Tsai , Fu-Hsiang Su , Ke-Jing Yu , Chih-Hong Hwang , Jyh-Huei Chen
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L29/417 , H01L21/48 , H01L21/768 , H01L23/522
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.

5. 发明申请

US20100240224A1 MULTI-ZONE SEMICONDUCTOR FURNACE 审中-公开
标题翻译：多区半导体炉
公开(公告)号：US20100240224A1
公开(公告)日：2010-09-23
申请号：US12408427
申请日：2009-03-20
申请人： Hsin-Hsien Wu , Chun-Lin Chang , Chi-Ming Yang
发明人： Hsin-Hsien Wu , Chun-Lin Chang , Chi-Ming Yang
IPC分类号： H01L21/26 , F27D11/00
CPC分类号： H01L21/67109 , F27B17/0025
摘要： A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of heaters arranged and operative to heat the chamber. The heating system includes at least one top heater; at least one bottom heater, and a plurality of sidewall heaters spaced along the height of the reaction chamber to control temperature variations within in the chamber and promote uniform film deposit thickness on the wafers.
摘要翻译：适用于晶圆化学气相沉积处理的半导体炉。该炉包括具有顶部，底部，侧壁和用于可拆卸地保持一批垂直堆叠的晶片的内部空腔的热反应室。提供一种加热系统，其包括布置并可操作以加热该腔室的多个加热器。加热系统包括至少一个顶部加热器; 至少一个底部加热器和沿着反应室的高度间隔开的多个侧壁加热器，以控制室内的温度变化，并促进晶片上均匀的膜沉积厚度。

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