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1. 发明申请

WO1998024028A1 METHOD AND SYSTEM FOR MANAGING A FLASH MEMORY MASS STORAGE SYSTEM 审中-公开
标题翻译：用于管理闪存存储大容量存储系统的方法和系统
公开(公告)号：WO1998024028A1
公开(公告)日：1998-06-04
申请号：PCT/US1996018972
申请日：1996-11-26
申请人： MACRONIX INTERNATIONAL CO., LTD. , MA, Chung-Wen , LIN, Chun-Hung , LEE, Tai-Yao , LEE, Li-Jen , LEE, Ju-Xu , HU, Ting-Chung
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G06F12/06
CPC分类号： G11C29/765 , G06F3/0616 , G06F3/0652 , G06F3/0679 , G06F11/1068 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/349 , G11C16/3495
摘要： Methods for managing a mass storage system (100) including a flash memory having first (172-174), second (176-177) and third (181-183) types of blocks which may be changed from one type to another type, are disclosed. A "wear-leveling" procedure (400) may be used in which the difference in the number of times of erasure of any two blocks, except defective blocks, is within a predetermined value. The blocks are divided into a plurality of sectors (350), each sector having a start portion (352), a data portion (354), and an end portion (356). A sector is marked valid only when the start and end portions contain a predetermined pattern of data, and is marked clean when no data has been written into the start and end portions. Data may be stored in two separate memory locations, and an "OR" or "AND" operation performed to recover the data.
摘要翻译：用于管理大容量存储系统（100）的方法包括具有可以从一种类型改变到另一种类型的第一（172-174），第二（176-177）和第三（181-183）类型的块的闪存，披露。可以使用除了缺陷块以外的任何两个块的擦除次数的差异在预定值内的“磨损均衡”过程（400）。这些块被分成多个扇区（350），每个扇区具有起始部分（352），数据部分（354）和端部（356）。扇区仅在起始端和端部包含预定数据模式时被标记为有效，并且当没有数据被写入到开始和结束部分时被标记为干净。数据可以存储在两个单独的存储器位置中，并且执行“OR”或“AND”操作来恢复数据。

2. 发明申请

WO1998019343A1 MEMORY REDUNDANCY CIRCUIT USING SINGLE POLYSILICON FLOATING GATE TRANSISTORS AS REDUNDANCY ELEMENTS 审中-公开
标题翻译：使用单个多晶硅浮动栅极晶体管作为冗余元件的存储器冗余电路
公开(公告)号：WO1998019343A1
公开(公告)日：1998-05-07
申请号：PCT/US1996017300
申请日：1996-10-28
申请人： MACRONIX INTERNATIONAL CO., LTD. , YIU, Tom, Dang-Hsing , SHONE, Fuchia
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： H01L29/76
CPC分类号： G11C29/80 , G11C29/822 , H01L27/115 , H01L29/7885
摘要： A read-only memory device (10) is provided which comprises an array of read-only memory cells arranged in rows and columns. An additional row (15) of flat, single polysilicon floating gate memory cells is provided. A row decoder (11) coupled to the array of read-only memory cells is responsive to addresses corresponding to rows in the array for selecting addressed rows. Control circuitry (18) including a programmable store for identifying a defective row in the array to be replaced by the additional row, selects the additional row and replaces the defective row in response to an address corresponding to the defective row. In addition, circuitry (19) is provided on the integrated circuit which allows access to the additional row of floating gate memory cells for programming the additional row. This structure is particularly applied to an array of mask ROM cells.
摘要翻译：提供了只读存储器件（10），其包括以行和列排列的只读存储器单元的阵列。提供了另外一排（15）平坦的单个多晶硅浮动栅极存储单元。耦合到只读存储器单元阵列的行解码器（11）响应于对应于阵列中的行的地址来选择寻址行。控制电路（18）包括一个可编程存储器，用于识别阵列中由附加行替代的有缺陷的行，选择附加行并响应于与该有缺陷行相对应的地址替换该有缺陷行。此外，在集成电路上提供电路（19），其允许访问用于编程附加行的附加行的浮动栅极存储器单元。该结构特别适用于掩模ROM单元阵列。

3. 发明申请

WO1998011660A1 LOW VOLTAGE SUPPLY CIRCUIT 审中-公开
标题翻译：低电压电源
公开(公告)号：WO1998011660A1
公开(公告)日：1998-03-19
申请号：PCT/US1996014712
申请日：1996-09-11
申请人： MACRONIX INTERNATIONAL CO., LTD. , WAN, Ray-Lin , HUNG, Chun-Hsiung
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： H02M07/46
CPC分类号： G05F3/24
摘要： A low voltage supply circuit supplies an internal supply voltage in an integrated circuit, while consuming very little stand-by current, and providing substantial driving power to maintain the internal supply nodes at the desired voltage level. The low voltage supply circuit includes a first branch and a second branch. The first branch includes a pull-up circuit (11), a first transistor (18), a second transistor (19), and a reference circuit (14), connected in series. The drain and the gate of the first transistor (18) are connected to a first node (13). The pull-up circuit (11) in the first branch is coupled between the first node (13) and power supply node (12). The drain and the gate of the second transistor (19), are connected to a second node (15). The reference circuit (14) is connected between ground supply node (34) of the integrated circuit and the second node (15), supplying a reference potential to the second node (15).
摘要翻译：低电压电源电路在集成电路中提供内部电源电压，同时消耗很少的待机电流，并提供实质的驱动功率以将内部供电节点维持在期望的电压电平。低电压电路包括第一分支和第二分支。第一分支包括串联连接的上拉电路（11），第一晶体管（18），第二晶体管（19）和参考电路（14）。第一晶体管（18）的漏极和栅极连接到第一节点（13）。第一分支中的上拉电路（11）耦合在第一节点（13）和电源节点（12）之间。第二晶体管（19）的漏极和栅极连接到第二节点（15）。参考电路（14）连接在集成电路的接地电源节点（34）和第二节点（15）之间，为第二节点（15）提供参考电位。

4. 发明申请

WO1998011607A1 STACKED READ-ONLY MEMORY 审中-公开
标题翻译：堆叠的只读存储器
公开(公告)号：WO1998011607A1
公开(公告)日：1998-03-19
申请号：PCT/US1996014685
申请日：1996-09-10
申请人： MACRONIX INTERNATIONAL CO., LTD. , SHONE, Fu-Chia , YIU, Tom, Dang-Hsing
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： H01L29/76
CPC分类号： H01L27/1128 , H01L27/112
摘要： A stacked ROM device utilizes the same conductivity type for the ROM cells in both the top (11) and the bottom (12) ROM cell matrixes. The stacked ROM device comprises a first ROM cell matrix (12) which comprises conductively doped source and drain lines having a first conductivity type in a semiconductor substrate having a second conductivity type. For example, the source and drain lines are implemented with n-type doping in a p-type substrate. A second ROM cell matrix (11) comprises conductivity doped source and drain lines having the first conductivity type in a semiconductor layer which overlies and is isolated from the semiconductor substrate (10). A plurality of shared wordlines (15) is deposed between the first (12) and second (11) ROM cell matrixes. A plurality of bit lines (16) is isolated from and overlies the semiconductor layer. A plurality of matrix select transistors is coupled between the conductively doped source and drain lines in the first ROM cell matrix (12) and the plurality of bit lines (16), and between the conductively doped source and drain lines in the second ROM cell matrix (11) and the plurality of bit lines (16), to selectively connect the first ROM cell matrix (12) and the second ROM cell matrix (11) to the plurality of bit lines (16).
摘要翻译：堆叠的ROM器件对于顶部（11）和底部（12）ROM单元矩阵中的ROM单元使用相同的导电类型。堆叠的ROM器件包括第一ROM单元矩阵（12），其包括在具有第二导电类型的半导体衬底中具有第一导电类型的导电掺杂源极和漏极线。例如，源极和漏极线在p型衬底中用n型掺杂实现。第二ROM单元矩阵（11）包括在半导体层中覆盖并与半导体衬底（10）隔离的具有第一导电类型的导电掺杂源极和漏极线。多个共享字线（15）被放置在第一（12）和第二（11）个ROM单元矩阵之间。多个位线（16）与半导体层隔离并覆盖半导体层。多个矩阵选择晶体管耦合在第一ROM单元矩阵（12）和多个位线（16）中的导电掺杂源极线和漏极线之间以及第二ROM单元矩阵中的导电掺杂源极和漏极线之间（11）和多个位线（16），以将第一ROM单元矩阵（12）和第二ROM单元矩阵（11）选择性地连接到多个位线（16）。

5. 发明申请

WO1996028850A1 SERIES CAPACITOR CHARGE PUMP 审中-公开
标题翻译：系列电容充电泵
公开(公告)号：WO1996028850A1
公开(公告)日：1996-09-19
申请号：PCT/US1995003069
申请日：1995-03-09
申请人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION , KAMEI, Teruhiko , LEE, I-Long , SOEJIMA, Kouta , WAN, Ray-Lin
发明人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION
IPC分类号： H01L29/78
CPC分类号： H01L27/0222 , H02M3/073
摘要： A charge pump apparatus comprises first and second active capacitors (100/101) in series, having a common node (103) between them. The second lead of the second active capacitor (101) is coupled to a particular node (OUT) which drives an output of the charge pump. A pump clock (CLK0) is connected to the first lead of the first active capacitor (100). A voltage clamp (105) is connected to the particular node (OUT) and provides a bias point. A dynamic biasing circuit (108) is connected to the common node (103) and charges the common node (103) and the particular node (OUT) between transitions of the pump clock (CLK0) to keep both active capacitors (100/101) activated during the transitions. The dynamic biasing circuit (108) includes a precharge circuit (63/64) responsive to a charge clock (CLKB) wherein the charge clock (CLKB) has transitions non-overlapping with transitions of the pump clock (CLK0).
摘要翻译：电荷泵装置包括串联的第一和第二有源电容器（100/101），它们之间具有公共节点（103）。第二有源电容器（101）的第二引线耦合到驱动电荷泵的输出的特定节点（OUT）。泵时钟（CLK0）连接到第一有源电容器（100）的第一引线。电压钳（105）连接到特定节点（OUT）并提供偏置点。动态偏置电路（108）连接到公共节点（103），并且在泵时钟（CLK0）的转换之间对公共节点（103）和特定节点（OUT）充电以保持有源电容器（100/101）在转换期间激活。动态偏置电路（108）包括响应于充电时钟（CLKB）的充电电路（63/64），其中充电时钟（CLKB）具有与泵浦时钟（CLK0）的转换不重叠的转变。

6. 发明申请

WO1996008821A1 FLASH EPROM INTEGRATED CIRCUIT ARCHITECTURE 审中-公开
标题翻译：闪存EPROM集成电路架构
公开(公告)号：WO1996008821A1
公开(公告)日：1996-03-21
申请号：PCT/US1994010331
申请日：1994-09-13
申请人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION , YIU, Tom, Dang-Hsing , SHONE, Fuchia , LIN, Tien-Ler , WAN, Ray, L.
发明人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION
IPC分类号： G11C07/00
CPC分类号： G11C8/12 , G08G1/017 , G11C16/0491 , G11C16/10 , G11C16/16 , H01L27/115 , H01L27/11521
摘要： Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell (75-1, 75-n, 76-1, 76-n) is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and two N columns of flash EPROM cells. M word lines (WL1-WLN), each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines (83, 84) are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array.
摘要翻译：非接触式闪存EPROM单元和阵列设计及其制造方法产生密集，可分割的闪存EPROM芯片。闪存EPROM单元（75-1,75-n，76-1,76-n）基于漏 - 源 - 漏配置，其中单个源扩散由两列晶体管共享。该模块包括具有至少M行和两列N列闪速EPROM单元的存储器阵列。 M字线（WL1-WLN）各自耦合到闪存EPROM单元的M行之一中的闪存EPROM单元和N个全局位线（83,84）。数据输入和输出电路耦合到提供在存储器阵列中的数据读取和写入的N个全局位线。

7. 发明申请

WO1998024029A1 FLASH MEMORY MASS STORAGE SYSTEM 审中-公开
标题翻译：闪存存储大容量存储系统
公开(公告)号：WO1998024029A1
公开(公告)日：1998-06-04
申请号：PCT/US1996018973
申请日：1996-11-26
申请人： MACRONIX INTERNATIONAL CO., LTD. , MA, Chung-Wen , LIN, Chun-Hung , LEE, Tai-Yao , LEE, Li-Jen , LEE, Ju-Xu , HU, Ting-Chung
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G06F12/06
CPC分类号： G06F3/0616 , G06F3/0656 , G06F3/0679 , G06F12/0246 , G06F2212/7203
摘要： An architecture for a mass storage system using flash memory involves organizing the flash memory into a plurality of blocks which are then divided into several categories (181-183, 172-174, 177-176). There are three categories of blocks: 1) working category (172-174) used to store data organized in accordance with a pre-defined addressing scheme (such as the logical block address used in Microsoft's operating system), 2) temporary buffer used to store data intended to be written to one of the working blocks (176), and 3) blocks that need to be erased (181-183). When data is written into the mass storage system, a block in the second category (176) is allocated from a block in the third category (181-183). The allocated block will then be changed to a block in the first category when writing to the allocated block is completed (172-174). The corresponding block in the first category is placed into the third category (e.g. 172).
摘要翻译：使用闪速存储器的大容量存储系统的架构涉及将闪存组织成多个块，然后将这些块分成几个类别（181-183,172-174,177-176）。有三种类型的块：1）用于存储根据预定义寻址方案（例如Microsoft操作系统中使用的逻辑块地址）组织的数据的工作类别（172-174），2）用于存储要写入其中一个工作块（176）的数据，以及3）需要擦除的块（181-183）。当数据被写入大容量存储系统时，第二类别（176）中的块从第三类别（181-183）中的块分配。然后，当写入分配的块完成时，分配的块将被改变为第一类中的块（172-174）。第一类别中的相应块被放置在第三类（例如172）中。

8. 发明申请

WO1998010471A1 TRIPLE WELL FLOATING GATE MEMORY AND OPERATING METHOD WITH ISOLATED CHANNEL PROGRAM, PREPROGRAM AND ERASE PROCESSES 审中-公开
标题翻译：具有隔离通道程序，预处理和擦除过程的三阱井浮动存储器和操作方法
公开(公告)号：WO1998010471A1
公开(公告)日：1998-03-12
申请号：PCT/US1996014349
申请日：1996-09-05
申请人： MACRONIX INTERNATIONAL CO., LTD. , HUNG, Chun-Hsiung , SHIAU, Tzeng-Huei , WAN, Ray-Lin , SHONE, Fu-Chia
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： H01L29/788
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A floating gate memory cell having a first well (31), second well (30) source/drain regions (13/14), a floating gate (15), a control gate (17) and circuits to induce tunneling of electrons from the floating gate into the channel area.
摘要翻译：一种具有第一阱（31），第二阱（30）源极/漏极区域（13/14），浮动栅极（15），控制栅极（17）以及电子从浮动通道进入通道区域。

9. 发明申请

WO1996038845A1 TECHNIQUE FOR RECONFIGURING A HIGH DENSITY MEMORY 审中-公开
标题翻译：重建高密度存储器的技术
公开(公告)号：WO1996038845A1
公开(公告)日：1996-12-05
申请号：PCT/US1995006990
申请日：1995-05-31
申请人： MACRONIX INTERNATIONAL CO., LTD. , LIOU, Kong-Mou , YIU, Tom, Dang-Hsing , WAN, Ray-Lin , CHENG, Yao-Wu , HUNG, Chun-Hsiung , LIN, Tien-Ler , HU, Ting-Chung
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G11C07/00
CPC分类号： G11C29/76 , G11C8/08 , G11C8/10 , G11C8/12 , G11C16/08
摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated memory array having a plurality of sectors (10) selected by an address decoder (11, 13) in response to an N bit field in an address (17). If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder (12) to prevent access to the defective sectors while maintaining sequential addressing remaining in the array. The step of partitioning includes configuring the sector decoder (12) to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the address bits in common with the defective sector when m is between 1 and N-1.
摘要翻译：用于提高高密度存储器件（例如闪速EEPROM）的制造成品率的灵活技术涉及重新配置具有响应于N位的地址解码器（11,13）选择的多个扇区（10）的集成存储器阵列字段中的一个地址（17）。如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器（12）来分区以禁用缺陷扇区，以阻止对缺陷扇区的访问，同时保持阵列中的顺序寻址。分割步骤包括配置扇区解码器（12），以便当m在1之间时，具有与缺陷扇区相同的地址位的Nm的阵列的另一半中的阵列的一半中的缺陷扇区和N-1。

10. 发明申请

WO1996023307A1 DECODED WORDLINE DRIVER WITH POSITIVE AND NEGATIVE VOLTAGE MODES 审中-公开
标题翻译：具有正负电压模式的解码信号驱动器
公开(公告)号：WO1996023307A1
公开(公告)日：1996-08-01
申请号：PCT/US1995001031
申请日：1995-01-26
申请人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION , YIU, Tom, Dang-Hsing , KAMEI, Teruhiko , HUNG, Chun-Hsiung , WAN, Ray-Lin , CHENG, Yao-Wu
发明人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION
IPC分类号： G11C11/40
CPC分类号： G11C16/08 , G11C5/143 , G11C8/08 , G11C16/12
摘要： Wordline drive circuitry drives a plurality of wordlines (WL) in a flash EEPROM memory array. A first supply voltage selector (309) supplies positive voltage during a first mode, and a second mode reference voltage, such as ground, in a second mode. A second supply voltage selector (310) supplies the first mode reference voltage such as ground in the first mode, and a negative voltage during a second mode. An inverting driver (300) has an input (302) which receives a wordline select signal, and an output (301) coupled to the wordline, a first supply voltage input connected to the first supply voltage selector and second supply voltage input connected to the second supply voltage selector. The inverting driver (300) couples the first supply voltage input to the wordline when the wordline select signal is in a low state, and couples the second supply voltage input to the wordline when the wordline select signal is in a high state. A second inverter (308) is connected in feedback across the inverting driver (300) to hold the input of the inverting driver at the value of the wordline select signal during the negative voltage decode.
摘要翻译：字线驱动电路驱动闪存EEPROM存储器阵列中的多个字线（WL）。第一电源电压选择器（309）在第一模式下提供正电压，并在第二模式中提供诸如地的第二模式参考电压。第二电源电压选择器（310）在第一模式下提供诸如接地的第一模式参考电压和在第二模式期间的负电压。反相驱动器（300）具有接收字线选择信号的输入端（302）和耦合到字线的输出端（301），连接到第一电源电压选择器的第一电源电压输入端和连接到第一电源电压输入端的第二电源电压输入端第二电源电压选择器。当字线选择信号处于低状态时，反相驱动器（300）将第一电源电压输入耦合到字线，并且当字线选择信号处于高状态时，将第二电源电压输入耦合到字线。第二反相器（308）通过反相驱动器（300）反馈连接，以在负电压解码期间将反相驱动器的输入保持在字线选择信号的值。

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