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1. 发明申请

WO1995009424A1 AUTOMATIC TEST CIRCUITRY WITH NON-VOLATILE STATUS WRITE 审中-公开
标题翻译：自动测试电路与非易失性状态写入
公开(公告)号：WO1995009424A1
公开(公告)日：1995-04-06
申请号：PCT/US1993009317
申请日：1993-09-30
申请人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION , LIN, Tien-Ler , YIU, Tom, Dang-Hsing , WAN, Ray, L. , LIOU, Kong-Mou
发明人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/44
摘要： An integrated circuit (1) comprises a functional module (2) such as a FLASH memory with automatic program and erase circuits, test circuitry (3) coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuitry in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port (5) is provided on the integrated circuit coupled to the non-volatile memory (4) through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.
摘要翻译：集成电路（1）包括诸如具有自动编程和擦除电路的闪速存储器的功能模块（2），与功能模块耦合的测试电路（3），其执行功能模块的测试并产生状态信息的测试和非易失性状态写入电路与芯片上的测试电路耦合。非易失性状态写入电路中的电路响应于功能电路的测试，以将状态信息写入非易失性存储器。在集成电路上提供端口（5），该集成电路耦合到非易失性存储器（4），存储在非易失性存储器中的状态信息可通过该端口以测试读取模式访问到外部设备。在FLASH EPROM实施例中，IC包括闪存EPROM存储器单元阵列和阵列中的数据可由外部设备访问的端口。阵列中提供了一组FLASH EPROM存储单元。耦合到阵列的编程和擦除电路具有运行程序和擦除电路的测试模式，以产生指示测试结果的状态信息和测试读取模式以读出状态信息。非易失性状态写入电路耦合到程序和擦除电路和测试集，并将状态信息写入测试集。程序和擦除电路包括具有可编程阈值的重试计数，以减少器件的测试时间。

2. 发明申请

WO1996038845A1 TECHNIQUE FOR RECONFIGURING A HIGH DENSITY MEMORY 审中-公开
标题翻译：重建高密度存储器的技术
公开(公告)号：WO1996038845A1
公开(公告)日：1996-12-05
申请号：PCT/US1995006990
申请日：1995-05-31
申请人： MACRONIX INTERNATIONAL CO., LTD. , LIOU, Kong-Mou , YIU, Tom, Dang-Hsing , WAN, Ray-Lin , CHENG, Yao-Wu , HUNG, Chun-Hsiung , LIN, Tien-Ler , HU, Ting-Chung
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G11C07/00
CPC分类号： G11C29/76 , G11C8/08 , G11C8/10 , G11C8/12 , G11C16/08
摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated memory array having a plurality of sectors (10) selected by an address decoder (11, 13) in response to an N bit field in an address (17). If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder (12) to prevent access to the defective sectors while maintaining sequential addressing remaining in the array. The step of partitioning includes configuring the sector decoder (12) to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the address bits in common with the defective sector when m is between 1 and N-1.
摘要翻译：用于提高高密度存储器件（例如闪速EEPROM）的制造成品率的灵活技术涉及重新配置具有响应于N位的地址解码器（11,13）选择的多个扇区（10）的集成存储器阵列字段中的一个地址（17）。如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器（12）来分区以禁用缺陷扇区，以阻止对缺陷扇区的访问，同时保持阵列中的顺序寻址。分割步骤包括配置扇区解码器（12），以便当m在1之间时，具有与缺陷扇区相同的地址位的Nm的阵列的另一半中的阵列的一半中的缺陷扇区和N-1。

3. 发明申请

WO1997044792A1 FLASH MEMORY DEVICE WITH MULTIPLE CHECKPOINT ERASE SUSPEND LOGIC 审中-公开
标题翻译：具有多个检测点擦除功能的FLASH存储器件SUSPEND LOGIC
公开(公告)号：WO1997044792A1
公开(公告)日：1997-11-27
申请号：PCT/US1996007491
申请日：1996-05-22
申请人： MACRONIX INTERNATIONAL CO., LTD. , SHIAU, Tzeng-Huei , WAN, Ray, Lin , CHUANG, Weitong , LEE, Yu-Sui , LIOU, Kong, Mou
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C2216/20
摘要： A flash memory device (10) includes a multiple checkpoint erase suspend algorithm. A user may issue an erase suspend command at any time during an erase process. Erase suspend logic (15) is coupled to an erase logic (12) and executes an erase suspend procedure which interrupts the block erase procedure after receiving the erase suspend commande during the first to occur of a set of checkpoints in the block erase procedure. After interrupting the block erase procedure, the erase suspend procedure includes returning to the block erase procedure to complete the block erase.
摘要翻译：闪存设备（10）包括多检查点擦除挂起算法。用户可以在擦除过程中随时发出擦除挂起命令。擦除暂停逻辑（15）耦合到擦除逻辑（12），并且执行擦除暂停过程，该擦除暂停过程在块擦除过程中的一组检查点的第一次发生之后接收到擦除暂停命令之后中断块擦除过程。在中断块擦除过程之后，擦除暂停过程包括返回到块擦除过程以完成块擦除。

4. 发明申请

WO1996021227A1 ADVANCED PROGRAM VERIFY FOR PAGE MODE FLASH MEMORY 审中-公开
标题翻译：高级程序验证页面模式闪存
公开(公告)号：WO1996021227A1
公开(公告)日：1996-07-11
申请号：PCT/US1995000077
申请日：1995-01-05
申请人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION , LIN, Tien-Ler , HUNG, Chun-Hsiung , SOEJIMA, Kota , TAKAHASHI, Jun , LIOU, Kong-Mou , WAN, Ray-Lin
发明人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION
IPC分类号： G11C11/40
CPC分类号： G11C16/3445 , G11C16/0491 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2216/14
摘要： Flash EEPROM cell and array designs, and methods for programming the same result in efficient and accurate programming of a flash EEPROM chip. The flash EEPROM chip comprises a memory array (170) including at least M rows and N columns of flash EEPROM cells. M word lines (172) are each coupled to the flash EEPROM cells in one of the M rows of flash EEPROM cells. A plurality of bit lines (174) are each coupled to the flash EEPROM cells in one of the N columns of flash EEPROM cells. A page buffer (190) coupled to the plurality of bit lines supplies input data to N columns of flash EEPROM cells. Write control circuitry supplies programming voltages for programming input data to the flash EEPROM cells in response to the input data stored in the data input buffer (191). Verify circuity automatically verifies programming of the page by resetting bits in the page buffer for each cell which passes.
摘要翻译：闪存EEPROM单元和阵列设计，以及用于编程相同结果的方法用于快速和准确地编程闪存EEPROM芯片。快闪EEPROM芯片包括至少包括M行和N列快闪EEPROM单元的存储器阵列（170）。 M个字线（172）各自耦合到M行的快闪EEPROM单元之一中的快闪EEPROM单元。多个位线（174）各自连接到N列快闪EEPROM单元之一中的快闪EEPROM单元。耦合到多个位线的页缓冲器（190）将快速EEPROM单元的输入数据提供给N列。响应于存储在数据输入缓冲器（191）中的输入数据，写控制电路提供用于将输入数据编程到闪存EEPROM单元的编程电压。验证电路通过为通过的每个单元的页面缓冲器中的位重置来自动验证页面的编程。

5. 发明申请

WO1999033057A1 TECHNIQUE FOR INCREASING ENDURANCE OF INTEGRATED CIRCUIT MEMORY 审中-公开
标题翻译：增加集成电路存储器的耐用性的技术
公开(公告)号：WO1999033057A1
公开(公告)日：1999-07-01
申请号：PCT/US1997024146
申请日：1997-12-23
申请人： MACRONIX INTERNATIONAL CO., LTD. , LIOU, Kong-Mou , HU, Ting-Chung , WAN, Ray-Lin , SHONE, Fuchia
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G11C07/00
CPC分类号： G11C16/3495 , G11C16/349
摘要： A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors (30), and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array (10). A record (29) is maintained indicating one of the plurality of sectors (30) as a current sector, directing accesses using the subset of addresses to the current sector, counting changes excuted to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.
摘要翻译：一种方法提高了存储器单元阵列的耐久性，其具有根据存储器单元在性能容限内可以承受的变化周期的数量来指定的耐久性。该方法基于将阵列布置成多个扇区（30），并且分配用于存储数据结构的地址子集，预期将改变足以超过阵列中的存储器单元的规定耐久性的次数（10）。保持指示多个扇区（30）中的一个作为当前扇区的记录（29），将使用地址子集的访问定向到当前扇区，对从当前扇区的地址子集识别的存储器单元进行计数改变并且当所述改变的计数超过所述阈值时，将所述当前扇区改变为所述多个扇区中的另一个扇区。

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