专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

WO1996026585A1 DEVICE FOR RECOVERING A CLOCK FROM A MODULATED OPTICAL INPUT SIGNAL 审中-公开
标题翻译：安排从调制光INPUT A TIME恢复时钟
公开(公告)号：WO1996026585A1
公开(公告)日：1996-08-29
申请号：PCT/DE1996000241
申请日：1996-02-15
申请人： SIEMENS AKTIENGESELLSCHAFT , CREMER, Cornelius
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H04L07/00
CPC分类号： H04L7/0075
摘要： A laser device for recovering a clock from a modulated optical input signal (So) has a bi-directional optical transmission channel (3) that extends between a resonator mirror (21) for launching-in the input signal and a resonator mirror (42) for coupling-out the recovered clock (T). The transmission channel (3) has at least two non-linear optical amplifiers (2, 4) and a demultiplexer (6) arranged between the amplifiers. This device is operated as a mode-locked laser and is suitable for optical repeaters.
摘要翻译：用于从调制光输入信号（SO）回收时间时钟的激光装置具有，一个谐振器镜（21），用于对所恢复的时钟（T）的双向光传输信道耦合的输入信号和谐振器反射镜（42）之间的耦合（3）具有至少两个非线性光放大器（2,4）和所述放大器之间的多路分解器（6）。该装置操作为一个卷曲模式激光，适合于光中继器。

82. 发明申请

WO1996007255A1 DEVICE AND METHOD FOR EFFICIENT TIMING ESTIMATION IN A DIGITAL RECEIVER 审中-公开
标题翻译：数字接收机中有效时序估计的设备和方法
公开(公告)号：WO1996007255A1
公开(公告)日：1996-03-07
申请号：PCT/US1995008276
申请日：1995-06-30
申请人： MOTOROLA INC.
发明人： MOTOROLA INC. , GURNEY, David, Paul , BALM, Kevin, Lynn
IPC分类号： H04L07/00
CPC分类号： H04L7/0054 , H04B7/082 , H04L7/0083
摘要： The present invention provides for economical predictive symbol timing estimation in a digital receiver by reducing gate count and current drain. The invention also reduces the processing delay. The predictive symbol timing estimation method (300) and device (200) are applicable to any digital radio system which transmits on a continuous or semi-continuous basis.
摘要翻译：本发明通过减少门数和电流消耗来提供数字接收机中经济的预测符号定时估计。本发明还减少了处理延迟。预测符号定时估计方法（300）和装置（200）可应用于以连续或半连续方式发送的任何数字无线电系统。

83. 发明申请

WO1995010903A1 CORRELATION DETECTOR AND COMMUNICATION APPARATUS 审中-公开
标题翻译：相关检测器和通信设备
公开(公告)号：WO1995010903A1
公开(公告)日：1995-04-20
申请号：PCT/JP1994001715
申请日：1994-10-13
申请人： NTT MOBILE COMMUNICATIONS NETWORK INC. , DOHI, Tomohiro , SAWAHASHI, Mamoru , ADACHI, Fumiyuki
发明人： NTT MOBILE COMMUNICATIONS NETWORK INC.
IPC分类号： H04L07/00
CPC分类号： H04B1/7085 , H04B7/2125
摘要： A correlation detector for CDMA communication receivers, which can establish synchronization at a high speed, can extract mutually correlated components, and can perform highly accurate tracking. The received signal (21) is fed to a matched filter (43) when the initial synchronization is established. When a synchronization judging circuit (45) judges that the filter (43) detects synchronization, the switching circuit (42) feeds the signal (21) to multipliers (47, 48), and resets a VCCG (29) and a spread-spectrum code replica generator (30). After the synchronization is established, the spread-spectrum signal is detected quasi-synchronously, the received signal quasi-synchronously detected is multiplied by replical codes having advanced and lagged phases, and correlation detection signals are extracted from the multiplication results. The square components are generated, added together in opposite phases, and averaged in the time direction. The received spread-spectrum signal is multiplied by the codes whose phases are synchronous, and the results are integrated over chips. The signal, after the averaging processing, is reversely modulated by use of the identification signal of the received data obtained by compensation for the phase error of the received signal in order to generate a phase error signal. The replica code generator is driven by a clock the phase of which is controlled by the phase error signal.
摘要翻译：可以提供高速同步的CDMA通信接收机的相关检测器可以提取相互关联的组件，并且可以执行高精度的跟踪。当初始同步建立时，接收信号（21）被馈送到匹配滤波器（43）。当同步判断电路（45）判定滤波器（43）检测到同步时，切换电路（42）将信号（21）馈送到乘法器（47,48），并且复位VCCG（29）和扩展频谱代码副本生成器（30）。在同步建立之后，准同步检测扩频信号，准同步检测的接收信号与具有高级和滞后相位的复制码相乘，并从相乘结果中提取相关检测信号。生成平方分量，以相反的相位相加在一起，并在时间方向上平均。接收到的扩频信号乘以其相位同步的代码，并将结果集成在芯片上。在平均处理之后，通过使用通过对接收信号的相位误差进行补偿而获得的接收数据的识别信号来反向调制信号，以产生相位误差信号。复制码发生器由相位由相位误差信号控制的时钟驱动。

84. 发明申请

WO1995004415A1 DYNAMIC RADIO COMMUNICATIONS SYSTEM 审中-公开
标题翻译：动态无线电通信系统
公开(公告)号：WO1995004415A1
公开(公告)日：1995-02-09
申请号：PCT/US1993007237
申请日：1993-08-02
申请人： INTERNATIONAL STANDARD ELECTRIC CORP.
发明人： INTERNATIONAL STANDARD ELECTRIC CORP. , KENNEDY, John, B. , HEINEN, Joseph
IPC分类号： H04L07/00
CPC分类号： H04J15/00 , H04B7/18502 , H04J4/00
摘要： A communication system includes a plurality of subscribers each of said subscribers having a transceiver including a transmitter (34) and a receiver (35, 36). In the system there are means (31) coupled to each of said transceivers to enable said transmitter to transmit a unique waveform having a predetermined time, frequency and phase code and each transceiver includes means (32, 33) coupled to the receiver to enable anayone of said subscribers to receive any transmitted waveform while others of the subscribers including those receiving said waveform can simultaneously transmit other unique waveforms whereby any subscriber can receive any transmitted waveform while simultaneously transmitting another waveform.
摘要翻译：通信系统包括多个用户，每个所述用户具有收发器，该收发机包括发射机（34）和接收机（35,36）。在系统中，存在耦合到每个所述收发器的装置（31），以使得所述发射机能够发送具有预定时间，频率和相位码的唯一波形，并且每个收发器包括耦合到接收器的装置（32,33），以使得能够的所述用户接收任何发送的波形，而包括接收所述波形的用户的其他用户可以同时发送其他唯一波形，由此任何用户可以同时发送另一个波形而接收任何发送的波形。

85. 发明申请

WO1994000939A1 CIRCUIT FOR SIMULTANEOUS RECOVERY OF BIT CLOCK AND FRAME SYNCHRONIZATION 审中-公开
标题翻译：同步恢复时钟和帧同步的电路
公开(公告)号：WO1994000939A1
公开(公告)日：1994-01-06
申请号：PCT/US1993005846
申请日：1993-06-17
申请人： MOTOROLA INC.
发明人： MOTOROLA INC. , MESSERGES, Thomas, S. , DABBISH, Ezzat, A. , PUHL, Larry, C.
IPC分类号： H04L07/00
CPC分类号： H04J3/0602 , H04L7/042 , H04W28/06 , H04W84/12
摘要： Simultaneously detecting both frame (52, 54) synchronization in a serial bit stream reduces the time required to have a receiver lock up to a transmitted (100) serial data signal. A dual-phase correlator circuit is used to detect frame synchronization while a multiphase commutator (200) circuit detects bit clock synchronization.
摘要翻译：同时检测串行比特流中的帧（52,54）同步减少了将接收机锁定到传输的（100）串行数据信号所需的时间。当多相换向器（200）电路检测到位时钟同步时，使用双相位相关器电路来检测帧同步。

86. 发明申请

WO1993019547A1 PHASE ADJUSTMENT METHOD AND APPARATUS FOR USE IN A CLOCK RECOVERY CIRCUIT 审中-公开
标题翻译：在时钟恢复电路中使用的相位调整方法和装置
公开(公告)号：WO1993019547A1
公开(公告)日：1993-09-30
申请号：PCT/US1993000410
申请日：1993-01-21
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , LAROSA, Christopher, P. , CARNEY, Michael, J.
IPC分类号： H04L07/00
CPC分类号： H04L7/0062 , H04L7/0083
摘要： The present disclosure includes a discussion of a method of phase adjustment for use in a clock recovery scheme. The phase adjustment circuit automatically holds the clock phase during periods of poor channel quality. The clock recovery scheme generates a sampling clock signal (139) which is synchronous with the received signal (131). Additionally, the clock recovery scheme generates at least two error signals (347, 349, 351, 353) which indicate the quality of the received signal at different sampling phases. The smallest error signal is referred to as the minimum error value. Each error signal (347, 349, 351, 353) is compared to the minimum error value, creating a corresponding normalized error magnitude signal. Each normalized error magnitude signal is processed to determine the desired phase of the sampling clock signal. Dependent upon the processing of the normalized error magnitude signals, the phase of the sampling clock signal is either shifted or maintained until the next sampling point.

87. 发明申请

WO1993014585A1 FREQUENCY SYNCHRONIZED BIDIRECTIONAL RADIO SYSTEM 审中-公开
标题翻译：频率同步双向无线电系统
公开(公告)号：WO1993014585A1
公开(公告)日：1993-07-22
申请号：PCT/US1993000014
申请日：1993-01-08
申请人： DOMESTIC AUTOMATION COMPANY, INC.
发明人： DOMESTIC AUTOMATION COMPANY, INC. , DAVIDOV, Mircho, A. , FULTON, Forrest, F.
IPC分类号： H04L07/00
CPC分类号： H04W56/0035 , H04B1/408 , H04B1/56 , H04B7/2675 , H04J1/065 , H04L7/033 , H04L25/061 , H04L27/2332 , H04L27/3854 , H04L2027/0028 , H04L2027/0057
摘要： A bidirectional radio system for low cost, high through-put accumulation of data from a large number of site units. The site units are connected to remote radio transceivers in radio communication with a plurality of base stations (44). Accurate frequency synchronization allows multiple carriers within a 12.5 kHz FCC bandwidth. Frequency synchronization is achieved at low cost by transmitting a high accuracy carrier and clock signal at a base station, and using receiving circuitry (54) at remote stations to extract the base clock signal and base carrier frequency and a phase-lock loop (258 and 248) to stabilize the remote station carriers. The reception circuitry at a remote station provides independent carrier frequency and clock rate recovery, a phase-lock loop at baseband, and a coarse clock rate recovery circuit (316) coupled to a fine clock rate recovery circuit (320). Remote station responses are time domain multiplexed. A base station receiver can decode a very short remote station response by scaling the response with the phase and amplitude of an initial segment of the response. Spatial reuse of carrier frequencies further increases the rate of data throughout.
摘要翻译：一种双向无线电系统，用于低成本，高通量累积来自大量现场单元的数据。站点单元连接到与多个基站（44）的无线电通信中的远程无线电收发机。精确的频率同步允许12.5 kHz FCC带宽内的多个载波。通过在基站发送高精度载波和时钟信号，并且使用远端站处的接收电路（54）提取基本时钟信号和基本载波频率以及锁相环（258和 248）来稳定远程站运营商。远程站处的接收电路提供独立的载波频率和时钟速率恢复，基带处的锁相环和耦合到精细时钟速率恢复电路（320）的粗略时钟速率恢复电路（316）。远程站响应是时域复用的。基站接收机可以通过响应的初始段的相位和幅度缩放响应来解码非常短的远程站响应。载波频率的空间重用进一步提高了数据的速率。

88. 发明申请

WO1993004545A1 METHOD FOR SYNCHRONIZING SYNCHRONOUS DATA COMMUNICATION NETWORK, AND COMMUNICATION DEVICE USED IN THE NETWORK 审中-公开
标题翻译：用于同步同步数据通信网络的方法和网络中使用的通信设备
公开(公告)号：WO1993004545A1
公开(公告)日：1993-03-04
申请号：PCT/JP1992001042
申请日：1992-08-18
申请人： FUJITSU LIMITED , KOMURO, Yasuko , YAYIMA, Noboru , YOSHIDA, Hiroshi
发明人： FUJITSU LIMITED
IPC分类号： H04L07/00
CPC分类号： H04J3/0647 , H04J3/0641 , H04J2203/0042 , H04J2203/006 , H04J2203/0089 , H04Q11/0478
摘要： A method of switching synchronous signal sources of a synchronous data communication network having offices (A, B, C and D) connected to each other through circuits and synchronous signal sources installed inside and outside an office, in which even when a failure occurs in one of synchronizing signal sources, data communications are possible through switching the synchronizing signal sources to others according to the degree of the failure. Preset are flag bit data (S, *S), which indicate whether the synchronizing signal transmitted via the main wire is usable or not, in the signal including the synchronizing signal. When a failure occurs in one of the synchronizing signal sources, referring to the table specifying the priority order for selecting one synchronizing signal source, the table which is provided before-hand in every office, one synchronizing signal source is selected for every office according to the flag bit data. Then, in every office, the synchronizing signal source which has been selected at the present time is switched to a synchronizing signal source determined as mentioned above.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式