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81. 发明授权

US07876170B2 Frequency modulator, frequency modulating method, and wireless circuit 有权
标题翻译：频率调制器，频率调制方法和无线电路
公开(公告)号：US07876170B2
公开(公告)日：2011-01-25
申请号：US11790017
申请日：2007-04-23
申请人： Hisashi Adachi , Makoto Sakakura
发明人： Hisashi Adachi , Makoto Sakakura
IPC分类号： H03C3/06
CPC分类号： H03C3/0966 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03L7/1976 , H03M7/3022 , H03M7/3037 , H03M7/304 , H04L27/12
摘要： A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1. Therefore, it is possible to provide a frequency modulator that can use a reference signal source having no frequency modulation function, and perform modulation over a wide range of frequencies based on a digital modulation signal.
摘要翻译：压控振荡器1，可变分频器2，相位比较器3和环路滤波器4形成锁相环（PLL）。 Σ-Δ调制器5σ-Δ调制通过使用可变分频器2的输出信号作为时钟将分频因子数据的分数部分M2与调制数据X相加获得的数据。 Σ-Δ调制器5的输出信号被加到分频因子数据的整数部分M1上，结果数据成为可变分频器2的有效分频系数数据13.Σ-Δ调制器5的输出信号调制器5在通过D / A转换器6，低通滤波器7和幅度调整电路8之后也成为控制数据14.控制数据14被输入到压控振荡器1的调频端。因此，可以提供一种可以使用不具有频率调制功能的参考信号源的频率调制器，并且可以基于数字调制信号在宽范围的频率上进行调制。

82. 发明授权

US07777657B2 Sigma delta modulators 有权
标题翻译： Sigma delta调制器
公开(公告)号：US07777657B2
公开(公告)日：2010-08-17
申请号：US11995804
申请日：2006-06-29
申请人： Mark Brian Sandler , Joshua Daniel Reiss
发明人： Mark Brian Sandler , Joshua Daniel Reiss
IPC分类号： H03M3/00
CPC分类号： H03M7/3011 , H03M3/362 , H03M3/422 , H03M3/438 , H03M7/3037
摘要： A method is provided for detecting limit cycles in a sigma delta modulator having an output signal that varies over a series of time intervals. In this method a first value that is indicative of the level of the modulator output signal after a predetermined time interval is stored in a first memory, and a second value that is indicative of the level of the modulator output signal after a further time interval subsequent to the predetermined time interval is stored in a second memory. The first value stored in the first memory is compared with the second value stored in the second memory, and an output indicative of a tendency for limit cycles to be produced in the modulator output signal is provided in response to such comparison. Such a method is particularly advantageous for detecting limit cycles in a sigma delta modulator as it can be implemented in a straightforward manner and offers a very accurate limit cycle detection mechanism. As a result it only becomes necessary to activate a limit cycle removal mechanism when limit cycle behavior has been observed, and major changes to design are not normally required to implement the detection mechanism.
摘要翻译：提供了一种用于检测具有在一系列时间间隔上变化的输出信号的Σ-Δ调制器中的极限周期的方法。在该方法中，将指示预定时间间隔之后的调制器输出信号的电平的第一值存储在第一存储器中，以及指示后续时间间隔之后的调制器输出信号电平的第二值到预定时间间隔被存储在第二存储器中。存储在第一存储器中的第一值与存储在第二存储器中的第二值进行比较，并且响应于这种比较，提供表示在调制器输出信号中产生极限周期趋势的输出。这种方法对于在Σ-Δ调制器中检测极限循环特别有利，因为它可以以直接的方式实现并提供非常精确的极限循环检测机制。因此，仅当观察到极限循环行为时才需要激活极限循环去除机构，并且通常不需要对设计的主要改变来实现检测机制。

83. 发明授权

US07405685B2 Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权
标题翻译：使用反向时钟的发送缓冲器中的负贡献偏移补偿
公开(公告)号：US07405685B2
公开(公告)日：2008-07-29
申请号：US11178993
申请日：2005-07-11
申请人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
发明人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
IPC分类号： H03M3/00
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译：一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。来自Σ-Δ调制器的正输出的处理方式与负输出不同。与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。时钟的非反相版本与正输出一起使用，反向时钟与负输出一起使用。使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。结果是具有零偏移的偏移补偿RF输出信号。

84. 发明授权

US07330142B2 Sigma-delta modulator with a quantizer/gain element 失效
标题翻译：具有量化器/增益元件的Σ-Δ调制器
公开(公告)号：US07330142B2
公开(公告)日：2008-02-12
申请号：US10552779
申请日：2004-04-13
申请人： Erwin Janssen , Derk Reefman
发明人： Erwin Janssen , Derk Reefman
IPC分类号： H03M3/00
CPC分类号： H03M7/3035 , H03M3/43 , H03M3/444 , H03M3/452 , H03M3/454 , H03M7/3028 , H03M7/3037 , H03M7/304
摘要： A sigma-delta modulator (SDM) including n (n>_1) integrators in series, where a first of the n integrators receiving an input signal, at least one Q device, which acts as a quantizer when an absolute value of a signal input thereto is smaller and as a gain element (either with or without offset) when the absolute value of the signal input thereto is larger, and a device for quantizing an output of the unit. The SDM may be a feed back or feed forward SDM. The SDM may include a single or multiple Q devices. The single Q device may be positioned so that the signal input to the one Q device is an output of the last integrator and the output of the one device Q1 is input to the device for quantizing and/or to the n integrators. For multiple Q devices, each of the Q devices may have different parameters set to improve stability, improve SNR, and/or reduce introduction of artifacts. The SDM may be part of an analog to digital converter and/or a digital to digital converter. The SDM may process digital or analog signals, for example, a 1-bit signal.
摘要翻译：包括串联的n（n> _1）积分器的Σ-Δ调制器（SDM），其中接收输入信号的n个积分器中的第一个，至少一个Q器件，当信号输入的绝对值作为量化器时当其输入的信号的绝对值较大时，其较小，并且作为增益元件（有或没有偏移），以及用于量化该单元的输出的装置。 SDM可以是反馈或前馈SDM。 SDM可以包括单个或多个Q设备。单个Q设备可以被定位成使得输入到一个Q设备的信号是最后一个积分器的输出，并且一个设备Q 1的输出被输入到用于量化的设备和/或给n个集成商。对于多个Q设备，每个Q设备可以具有不同的参数来设置以提高稳定性，改善SNR，和/或减少伪像的引入。 SDM可以是模数转换器和/或数模转换器的一部分。 SDM可以处理数字或模拟信号，例如1位信号。

85. 发明申请

US20070200645A1 Frequency modulator, frequency modulating method, and wireless circuit 有权
标题翻译：频率调制器，频率调制方法和无线电路
公开(公告)号：US20070200645A1
公开(公告)日：2007-08-30
申请号：US11790017
申请日：2007-04-23
申请人： Hisashi Adachi , Makoto Sakakura
发明人： Hisashi Adachi , Makoto Sakakura
IPC分类号： H03C3/06 , H03C3/09
CPC分类号： H03C3/0966 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03L7/1976 , H03M7/3022 , H03M7/3037 , H03M7/304 , H04L27/12
摘要： A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1. Therefore, it is possible to provide a frequency modulator that can use a reference signal source having no frequency modulation function, and perform modulation over a wide range of frequencies based on a digital modulation signal.
摘要翻译：压控振荡器1，可变分频器2，相位比较器3和环路滤波器4形成锁相环（PLL）。 Σ-Δ调制器5σ-Δ调制通过使用可变分频器2的输出信号作为时钟将分频因子数据的分数部分M 2与调制数据X相加而获得的数据进行调制。 Σ-Δ调制器5的输出信号被加到分频系数数据的整数部分M 1，结果数据成为可变分频器2的有效分频系数数据13。 Σ-Δ调制器5的输出信号也经过D / A转换器6，低通滤波器7和振幅调整电路8后成为控制数据14。控制数据14被输入到压控振荡器1的调频终端。因此，可以提供一种可以使用不具有频率调制功能的参考信号源的频率调制器，并且可以在宽频率范围内进行调制基于数字调制信号。

86. 发明申请

US20070035424A1 Sigma-delta modulator 失效
标题翻译： Sigma-delta调制器
公开(公告)号：US20070035424A1
公开(公告)日：2007-02-15
申请号：US10552779
申请日：2004-04-13
申请人： Erwin Janssen , Derk Reefman
发明人： Erwin Janssen , Derk Reefman
IPC分类号： H03M3/00
CPC分类号： H03M7/3035 , H03M3/43 , H03M3/444 , H03M3/452 , H03M3/454 , H03M7/3028 , H03M7/3037 , H03M7/304
摘要： A sigma-delta modulator (SDM) including n (n>_1) integrators in series, where a first of the n integrators receiving an input signal, at least one Q device, which acts as a quantizer when an absolute value of a signal input thereto is smaller and as a gain element (either with or without offset) when the absolute value of the signal input thereto is larger, and a device for quantizing an output of the unit. The SDM may be a feed back or feed forward SDM. The SDM may include a single or multiple Q devices. The single Q device may be positioned so that the signal input to the one Q device is an output of the last integrator and the output of the one device Q, is input to the device for quantizing and/or to the n integrators. For multiple Q devices, each of the Q devices may have different parameters set to improve stability, improve SNR, and/or reduce introduction of artifacts. The SDM may be part of an analog to digital converter and/or a digital to digital converter. The SDM may process digital or analog signals, for example, a 1-bit signal.
摘要翻译：包括串联的n（n> _1）积分器的Σ-Δ调制器（SDM），其中接收输入信号的n个积分器中的第一个，至少一个Q器件，当信号输入的绝对值作为量化器时当其输入的信号的绝对值较大时，其较小，并且作为增益元件（有或没有偏移），以及用于量化该单元的输出的装置。 SDM可以是反馈或前馈SDM。 SDM可以包括单个或多个Q设备。单个Q器件可以被定位成使得输入到一个Q器件的信号是最后一个积分器的输出，并且一个器件Q的输出被输入到用于量化和/或向n个积分器的器件。对于多个Q设备，每个Q设备可以具有不同的参数来设置以提高稳定性，改善SNR，和/或减少伪像的引入。 SDM可以是模数转换器和/或数模转换器的一部分。 SDM可以处理数字或模拟信号，例如1位信号。

87. 发明申请

US20060284746A1 DIGITAL EXPANDER FOR GENERATING MULTIPLE ANALOG CONTROL SIGNALS PARTICULARLY USEFUL FOR CONTROLLING AN OSCILLATOR 有权
标题翻译：用于产生多个模拟控制信号的数字扩展器特别适用于控制振荡器
公开(公告)号：US20060284746A1
公开(公告)日：2006-12-21
申请号：US11461408
申请日：2006-07-31
申请人： Yunteng Huang , Bruno Garlepp , David Welland
发明人： Yunteng Huang , Bruno Garlepp , David Welland
IPC分类号： H03M7/00
CPC分类号： H03L7/093 , H03J2200/10 , H03L7/099 , H03L7/10 , H03L2207/06 , H03M7/3011 , H03M7/3028 , H03M7/3037
摘要： An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.
摘要翻译：示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

88. 发明授权

US07084710B2 Digital expander apparatus and method for generating multiple analog control signals particularly useful for controlling an oscillator 有权
标题翻译：用于产生对于控制振荡器特别有用的多个模拟控制信号的数字扩展器装置和方法
公开(公告)号：US07084710B2
公开(公告)日：2006-08-01
申请号：US10998521
申请日：2004-11-29
申请人： Yunteng Huang , Bruno W. Garlepp , David R. Welland
发明人： Yunteng Huang , Bruno W. Garlepp , David R. Welland
IPC分类号： H03L7/099
CPC分类号： H03L7/093 , H03J2200/10 , H03L7/099 , H03L7/10 , H03L2207/06 , H03M7/3011 , H03M7/3028 , H03M7/3037
摘要： An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.
摘要翻译：示例性PLL电路包括响应于多个子变容二极管控制信号的VCO。用于PLL的数字环路滤波器数字地生成变容二极管控制字，其被数字地扩展成多个数字值，每个数字值被传送到多个DAC中的对应的一个。复用器被配置为根据变容二极管控制字将DAC输出信号分别传送到一组子变容二极管控制信号，并且将剩余的子变容二极管控制信号驱动到满量程高值或满量程低 DAC输出的值。每个DAC优选地包括混合一阶/二阶Σ-Δ调制器，并且在某些实施例中，NRZ至RZ编码器电路和线性滤波器电路。

89. 发明授权

US07038606B2 Digital signal processing device and audio signal reproduction device 失效
标题翻译：数字信号处理装置和音频信号再生装置
公开(公告)号：US07038606B2
公开(公告)日：2006-05-02
申请号：US10507832
申请日：2003-10-23
申请人： Tsunehiko Hongoh , Hirotoshi Yamamoto
发明人： Tsunehiko Hongoh , Hirotoshi Yamamoto
IPC分类号： H03M3/00
CPC分类号： G11B20/10527 , G11B2020/00065 , H03M7/3035 , H03M7/3037
摘要： An audio signal reproduction device of the invention has a seventh-order delta-sigma modulation circuit that receives a PCM signal and that performs delta-sigma modulation on the PCM signal, a PWM circuit that performs pulse width modulation on the signal outputted from the seventh-order delta-sigma modulation circuit to produce a one-bit digital signal, a switching amplifier that converts the one-bit digital signal into an analog signal and that then amplifies it, and a low-pass filter that eliminates high-frequency components of the analog signal. This configuration permits size and weight reduction.
摘要翻译：本发明的音频信号再现装置具有接收PCM信号并对PCM信号执行Δ-Σ调制的七阶Δ-Σ调制电路，对从第七个输出的信号执行脉冲宽度调制的PWM电路用于产生1位数字信号的开关放大器，将1位数字信号转换为模拟信号，然后将其放大的开关放大器，以及消除高频分量的低通滤波器模拟信号。该配置允许尺寸和重量减轻。

90. 发明授权

US06965335B1 Methods for output edge-balancing in pulse width modulation systems and data converters using the same 有权
标题翻译：用于脉冲宽度调制系统中输出边沿平衡的方法和使用其的数据转换器
公开(公告)号：US06965335B1
公开(公告)日：2005-11-15
申请号：US10765443
申请日：2004-01-27
申请人： Brian David Trotter , Bruce Duewer , John Laurence Melanson
发明人： Brian David Trotter , Bruce Duewer , John Laurence Melanson
IPC分类号： H03M1/66 , H03M3/00 , H03M7/36
CPC分类号： H03M7/3006 , H02M2003/1586 , H03M3/506 , H03M7/3015 , H03M7/3026 , H03M7/3037
摘要： A method of performing digital to analog conversion includes generating a pulse width modulated data stream and another pulse width modulated data stream, encoding patterns of the pulse width modulated data stream selected to minimize distortion in the another pulse width modulated stream caused by edges in the pulse width modulated data stream. The pulse width modulated data stream and the another pulse width modulated data stream are converted into an analog signal and another analog signal converting in corresponding digital to analog conversion elements and the analog signal and the another analog signal are summed to generate an analog output signal.
摘要翻译：执行数模转换的方法包括生成脉冲宽度调制数据流和另一个脉宽调制数据流，编码脉宽调制数据流的模式，以选择最小化由脉冲中的边缘引起的另一个脉宽调制流中的失真宽度调制数据流。将脉冲宽度调制数据流和另一个脉冲宽度调制数据流转换成模拟信号，并在相应的数/模转换元件中转换另一个模拟信号，并将模拟信号和另一模拟信号相加以产生模拟输出信号。

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