基本信息:
- 专利标题： Frequency modulator, frequency modulating method, and wireless circuit
- 专利标题（中）：频率调制器，频率调制方法和无线电路
- 申请号：US11790017 申请日：2007-04-23
- 公开(公告)号：US20070200645A1 公开(公告)日：2007-08-30
- 发明人： Hisashi Adachi , Makoto Sakakura
- 申请人： Hisashi Adachi , Makoto Sakakura
- 优先权： JP2002-066884 20020312
- 主分类号： H03C3/06
- IPC分类号： H03C3/06 ; H03C3/09
摘要：
A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1. Therefore, it is possible to provide a frequency modulator that can use a reference signal source having no frequency modulation function, and perform modulation over a wide range of frequencies based on a digital modulation signal.
摘要（中）：
压控振荡器1，可变分频器2，相位比较器3和环路滤波器4形成锁相环（PLL）。 Σ-Δ调制器5σ-Δ调制通过使用可变分频器2的输出信号作为时钟将分频因子数据的分数部分M 2与调制数据X相加而获得的数据进行调制。 Σ-Δ调制器5的输出信号被加到分频系数数据的整数部分M 1，结果数据成为可变分频器2的有效分频系数数据13。 Σ-Δ调制器5的输出信号也经过D / A转换器6，低通滤波器7和振幅调整电路8后成为控制数据14。 控制数据14被输入到压控振荡器1的调频终端。因此，可以提供一种可以使用不具有频率调制功能的参考信号源的频率调制器，并且可以在宽频率范围内进行调制 基于数字调制信号。