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81. 发明专利

JP2007335860A Semiconductor structure and manufacturing method of semiconductor (semiconductor capacitor of hot (hybrid orientation technology) substrate) 有权
标题翻译：半导体的半导体结构与制造方法（半导体电容器（混合方向技术）衬底）
公开(公告)号：JP2007335860A
公开(公告)日：2007-12-27
申请号：JP2007150183
申请日：2007-06-06
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： RADENS CARL JOHN , RAMACHANDRA DIVAKARUNI , CHENG KANGGUO
IPC分类号： H01L21/822 , H01L27/04
CPC分类号： H01L29/945 , H01L29/66931
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor structure and a method for forming the same. SOLUTION: The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体结构及其形成方法。解决方案：半导体结构包括半导体衬底。半导体结构还包括在半导体衬底的顶部上的电绝缘区域。半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。半导体结构还包括在绝缘区域的顶部上的第二半导体区域。半导体结构还包括在第一半导体区域和半导体衬底中的电容器。半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。版权所有（C）2008，JPO＆INPIT

82. 发明授权

US11903331B2 Digital circuits comprising quantum wire resonant tunneling transistors 有权
公开(公告)号：US11903331B2
公开(公告)日：2024-02-13
申请号：US17467188
申请日：2021-09-04
申请人： Koucheng Wu
发明人： Koucheng Wu
IPC分类号： H10N60/10 , H10N60/01 , H10N69/00 , H03K19/20 , H03K19/088 , H03K19/00 , H03K19/082 , H03K17/60 , H01L29/04 , H01L29/66 , H01L29/76 , H01L29/15 , H01L29/775 , H03K17/92 , H03K19/195
CPC分类号： H10N60/128 , H01L29/045 , H01L29/151 , H01L29/66439 , H01L29/66931 , H01L29/7606 , H01L29/775 , H03K17/60 , H03K17/92 , H03K19/001 , H03K19/082 , H03K19/088 , H03K19/195 , H03K19/20 , H10N60/0884 , H10N69/00
摘要： A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.

83. 发明申请

US20170125557A1 METHOD OF MAKING A GRAPHENE BASE TRANSISTOR WITH REDUCED COLLECTOR AREA 审中-公开
公开(公告)号：US20170125557A1
公开(公告)日：2017-05-04
申请号：US15408813
申请日：2017-01-18
申请人： The Government of the United States of America, as represented by the Secretary of the Navy
发明人： Francis J. Kub , Travis J. Anderson , Andrew D. Koehler
IPC分类号： H01L29/737 , H01L29/16 , H01L29/08 , H01L29/66 , H01L29/10
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/1606 , H01L29/1608 , H01L29/165 , H01L29/2003 , H01L29/267 , H01L29/66037 , H01L29/66068 , H01L29/66242 , H01L29/66318 , H01L29/66931 , H01L29/66939 , H01L29/66969 , H01L29/732 , H01L29/7606
摘要： A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.

84. 发明授权

US09543423B2 Hot-electron transistor having multiple MSM sequences 有权
标题翻译：具有多个MSM序列的热电子晶体管
公开(公告)号：US09543423B2
公开(公告)日：2017-01-10
申请号：US14425403
申请日：2013-09-04
申请人： CARNEGIE MELLON UNIVERSITY
发明人： Yi Luo , Yixuan Chen , Rozana Hussin , Richard Carley
IPC分类号： H01L29/08 , H01L29/80 , H01L29/76 , H01L29/66 , H01L21/24 , H01L29/04 , H01L29/06 , H01L29/45
CPC分类号： H01L29/7606 , H01L21/24 , H01L29/04 , H01L29/0649 , H01L29/08 , H01L29/45 , H01L29/66931
摘要： In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The first semiconductor barrier separates the metal emitter and the metal base and has an average thickness based on a first mean free path of a charge carrier in the first semiconductor barrier emitted from the metal emitter. The second semiconductor barrier separates the metal base from the metal collector and has an average thickness based on a second mean free path of the charge carrier in the second semiconductor barrier injected from the metal base. The metal base comprises two or more metal layers and has an average thickness based on a multi-layer mean free path of the charge carrier.
摘要翻译：一方面，晶体管包括金属发射极，第一半导体势垒，金属基极，第二半导体势垒和金属集电极。第一半导体势垒分离金属发射极和金属基底，并且具有基于从金属发射体发射的第一半导体势垒中的载流子的第一平均自由程的平均厚度。第二半导体屏障将金属基底与金属集电体分开，并且具有基于从金属基底注入的第二半导体势垒中的电荷载体的第二平均自由程的平均厚度。金属基底包括两个或更多个金属层，并且具有基于电荷载体的多层平均自由程的平均厚度。

85. 发明申请

US20160372547A1 COLUMN IV TRANSISTORS FOR PMOS INTEGRATION 审中-公开
标题翻译：用于PMOS整合的柱IV晶体管
公开(公告)号：US20160372547A1
公开(公告)日：2016-12-22
申请号：US15255902
申请日：2016-09-02
申请人： INTEL CORPORATION
发明人： GLENN A. GLASS , ANAND S. MURTHY
IPC分类号： H01L29/06 , H01L23/535 , H01L29/36 , H01L29/417
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
摘要翻译：公开了用于形成具有高浓度锗的源/漏区的列IV晶体管器件的技术，并且相对于常规器件显示降低的寄生电阻。在一些示例性实施例中，源极/漏极区域各自包括薄的p型硅或锗或SiGe沉积，源/漏材料的其余部分沉积为p型锗或锗合金（例如锗：锡或其他合适的应变诱导剂，并且锗含量为至少80原子％和20原子％以下的其他组分）。在某些情况下，可以在富锗盖层中观察到应变松弛的证据，包括失配位错和/或穿透位错和/或双胞胎。可以使用多个晶体管配置，包括平面和非平面晶体管结构（例如，FinFET和纳米线晶体管），以及应变和非限制的通道结构。

86. 发明申请

US20150255588A1 HOT-ELECTRON TRANSISTOR HAVING METAL TERMINALS 有权
标题翻译：具有金属端子的热电子晶体管
公开(公告)号：US20150255588A1
公开(公告)日：2015-09-10
申请号：US14425403
申请日：2013-09-04
申请人： CARNEGIE MELLON UNIVERSITY
发明人： Yi Luo , Yixuan Chen , Rozana Hussin , Richard Carley
IPC分类号： H01L29/76 , H01L29/45 , H01L21/24 , H01L29/08 , H01L29/06 , H01L29/66 , H01L29/04
CPC分类号： H01L29/7606 , H01L21/24 , H01L29/04 , H01L29/0649 , H01L29/08 , H01L29/45 , H01L29/66931
摘要： In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The first semiconductor barrier separates the metal emitter and the metal base and has an average thickness based on a first mean free path of a charge carrier in the first semiconductor barrier emitted from the metal emitter. The second semiconductor barrier separates the metal base from the metal collector and has an average thickness based on a second mean free path of the charge carrier in the second semiconductor barrier injected from the metal base. The metal base comprises two or more metal layers and has an average thickness based on a multi-layer mean free path of the charge carrier.
摘要翻译：一方面，晶体管包括金属发射极，第一半导体势垒，金属基极，第二半导体势垒和金属集电极。第一半导体势垒分离金属发射极和金属基底，并且具有基于从金属发射体发射的第一半导体势垒中的载流子的第一平均自由程的平均厚度。第二半导体屏障将金属基底与金属集电体分开，并且具有基于从金属基底注入的第二半导体势垒中的电荷载体的第二平均自由程的平均厚度。金属基底包括两个或更多个金属层，并且具有基于电荷载体的多层平均自由程的平均厚度。

87. 发明授权

US09076837B2 Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage 有权
标题翻译：具有低寄生BJT增益和稳定阈值电压的横向绝缘栅双极晶体管结构
公开(公告)号：US09076837B2
公开(公告)日：2015-07-07
申请号：US13543662
申请日：2012-07-06
申请人： Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
发明人： Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
IPC分类号： H01L29/49 , H01L29/739 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L29/66325 , H01L21/8222 , H01L29/0634 , H01L29/0696 , H01L29/0808 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66931 , H01L29/7393 , H01L29/7394 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.
摘要翻译：本公开提供了金属氧化物半导体横向扩散器件（HV LDMOS），特别是横向绝缘栅双极结型晶体管（LIGBT）及其制造方法。该器件包括具有漂移区的漂移区绝缘体（SOI）衬底，漂移区中的两个相对掺杂的阱区，漂移区和第二阱区中的两个绝缘结构，第二阱区，栅极结构和源极在第二阱区域中的第三阱区域中嵌入第二阱区域。第三阱区域设置在栅极结构和第二绝缘结构之间。

88. 发明申请

US20140284552A1 GRAPHENE BASE TRANSISTOR WITH REDUCED COLLECTOR AREA 有权
标题翻译：具有减少收集区域的石墨基底晶体管
公开(公告)号：US20140284552A1
公开(公告)日：2014-09-25
申请号：US14178375
申请日：2014-02-12
申请人： Francis J. Kub , Travis J. Anderson , Andrew D. Koehler
发明人： Francis J. Kub , Travis J. Anderson , Andrew D. Koehler
IPC分类号： H01L29/16 , H01L29/66 , H01L29/737
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/1606 , H01L29/1608 , H01L29/165 , H01L29/2003 , H01L29/267 , H01L29/66037 , H01L29/66068 , H01L29/66242 , H01L29/66318 , H01L29/66931 , H01L29/66939 , H01L29/66969 , H01L29/732 , H01L29/7606
摘要： A graphene base transistor with reduced collector area comprising an electron injection region, an electron collection region, and a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.
摘要翻译：一种具有减小的集电极面积的石墨烯基晶体管，包括电子注入区域，电子收集区域和基极区域，其中所述基极区域包括一个或多个石墨烯片，并且其中所述基极区域在电子注入区域和电子收集区域之间并与其形成电接口。一种制造具有减小的集电极面积的石墨烯基晶体管的方法，包括形成电子注入区域，形成电子收集区域，以及形成基极区域，其中所述基极区域包括一片或多片石墨烯，并且其中所述基极区域位于所述电子注入区域和电子收集区域并与其形成电接口。

89. 发明授权

US08362462B2 Gated resonant tunneling diode 有权
标题翻译：门控谐振隧道二极管
公开(公告)号：US08362462B2
公开(公告)日：2013-01-29
申请号：US13024078
申请日：2011-02-09
申请人： Henry L. Edwards , Robert C. Bowen , Tathagata Chatterjee
发明人： Henry L. Edwards , Robert C. Bowen , Tathagata Chatterjee
IPC分类号： H01L29/06
CPC分类号： H01L29/882 , H01L27/0629 , H01L27/0811 , H01L29/107 , H01L29/66931
摘要： A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer.
摘要翻译：提供无低温冷却运行的门控谐振隧道二极管（GRTD）。该GRTD采用传统CMOS工艺技术，优选在65纳米节点和更小的不同于其他需要其他完全不同的工艺技术和操作条件的常规量子晶体管。为了实现这一点，GRTD使用在主体中形成的第一电极区域和第二电极区域（每个第二导电类型）的第一导电类型的主体。通道位于主体中的第一和第二电极区之间。在沟道中形成第一导电类型的阻挡区域（阻挡区域的掺杂水平大于主体的掺杂水平），以及在沟道中形成的第二导电类型的量子阱区域。此外，阻挡区域位于第一和第二电极区域和量子阱区域中的每一个之间。绝缘层形成在主体上，绝缘层在量子阱区域和阻挡区域的至少一部分上延伸，并且在绝缘层上形成控制电极区域。

90. 发明申请

US20110127572A1 GATED RESONANT TUNNELING DIODE 有权
标题翻译：嵌体共振隧道二极管
公开(公告)号：US20110127572A1
公开(公告)日：2011-06-02
申请号：US13024078
申请日：2011-02-09
申请人： Henry L. Edwards , Robert C. Bowen , Tathagata Chatterjee
发明人： Henry L. Edwards , Robert C. Bowen , Tathagata Chatterjee
IPC分类号： H01L29/15
CPC分类号： H01L29/882 , H01L27/0629 , H01L27/0811 , H01L29/107 , H01L29/66931
摘要： A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer.
摘要翻译：提供无低温冷却运行的门控谐振隧道二极管（GRTD）。该GRTD采用传统CMOS工艺技术，优选在65纳米节点和更小的不同于其他需要其他完全不同的工艺技术和操作条件的常规量子晶体管。为了实现这一点，GRTD使用在主体中形成的第一电极区域和第二电极区域（每个第二导电类型）的第一导电类型的主体。通道位于主体中的第一和第二电极区之间。在沟道中形成第一导电类型的阻挡区域（阻挡区域的掺杂水平大于主体的掺杂水平），以及在沟道中形成的第二导电类型的量子阱区域。此外，阻挡区域位于第一和第二电极区域和量子阱区域中的每一个之间。绝缘层形成在主体上，绝缘层在量子阱区域和阻挡区域的至少一部分上延伸，并且在绝缘层上形成控制电极区域。

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