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81. 发明专利

JPS5952847A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5952847A
公开(公告)日：1984-03-27
申请号：JP16552182
申请日：1982-09-20
申请人： Mitsubishi Electric Corp
发明人： ITAKURA HIDEAKI
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762
CPC分类号： H01L21/7621
摘要： PURPOSE:To enable to form a fine pattern by forming a groove surrounding the active region section of the semiconductor substrate, coating the side surface of a first thin-film coating the active region section and a section just under the thin-film with a third thin-film and forming an inter-element isolation region through thermal oxidation. CONSTITUTION:A first thin-film 12 is formed on the silicon semiconductor substrate 1, and first layer silicon nitride film 3 and underlay silicon oxide film 2 at a position where the isolation region is formed are removed. A polycrystalline silicon film 6 coating the whole surface of the substrate 1 and a molybdenum- silicide film 7 as a second thin-film 13 are formed. The U-shaped groove 8 is formed in the silicon semiconductor substrate 1 in the vicinity of a stepped difference section. The element isolation region is formed because a silicon oxide film 5 is formed selectively in the exposed region of the silicon semiconductor substrate 1 through thermal oxidation. The wall 10 of a remaining second layer silicon nitride film 9 and the first layer silicon nitride film 3 and underlay silicon oxide film 2 are removed in succession, and the surface of the silicon semiconductor substrate 1 is exposed.
摘要翻译：目的：为了通过形成围绕半导体衬底的有源区段的沟槽来形成精细图案，将第一薄膜的侧表面涂覆有活性区域部分和薄膜正下方的部分，第三薄膜薄膜，并通过热氧化形成元件间隔离区域。构成：在硅半导体衬底1上形成第一薄膜12，并且去除形成隔离区的位置上的第一层氮化硅膜3和底层氧化硅膜2。形成涂覆基板1的整个表面的多晶硅膜6和作为第二薄膜13的硅化钼膜7。 U形槽8形成在硅半导体衬底1中，在阶梯差分区域附近。由于通过热氧化在硅半导体衬底1的暴露区域中选择性地形成氧化硅膜5，所以形成元件隔离区。剩余的第二层氮化硅膜9的壁10和第一层氮化硅膜3和底衬氧化硅膜2被连续地去除，并且硅半导体衬底1的表面被暴露。

82. 发明专利

JPS58216438A Oxide film separating semiconductor device 失效
标题翻译：氧化物膜分离半导体器件
公开(公告)号：JPS58216438A
公开(公告)日：1983-12-16
申请号：JP10110782
申请日：1982-06-10
申请人： Mitsubishi Electric Corp
发明人： HIGUCHI TETSUO
IPC分类号： H01L29/73 , H01L21/316 , H01L21/331 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76216 , H01L21/7621
摘要： PURPOSE:To improve high frequency characteristic of a bipolar transistor by providing the n type semiconductors which are respectively placed in contact with the n type floating collectors of a pair of transistor forming regions isolated by an isolating oxide film and the p type channel cut layer which are held from both sides by these n type semiconductor layers and are placed in contact with them. CONSTITUTION:After forming an n type floating collector 2 on a p type Si substrate 1, a p type channel cut layer 5a is formed by diffusion or ion implantation in such a manner that it is not placed in contact with the n type floating collector 2. Thereafter, an n type Si epitaxial growth layer 3 is formed. In this case, distance between the p channel cut layer 5a and n type floating collector 2 should be as wide as allowing the n type Si layer 9 to remain between them even after the n type Si epitaxial growth layer 3 is formed. Thereafter, an isolation oxide film 4 is formed with the CVD nitride film 7 used as the mask and the n type Si layer 9 is left in both ends of the p type channel cut layer 5a just under such isolation oxide film 4.
摘要翻译：目的：通过提供分别与通过隔离氧化膜隔离的一对晶体管形成区域的n +型浮动集电极接触的n +型半导体来改善双极晶体管的高频特性，并且 p +型沟道切割层，由这些n +型半导体层从两侧保持并与它们接触。构成：在p型Si衬底1上形成n +型浮动集电器2之后，通过扩散或离子注入形成ap +型沟道切割层5a，使得其不被接触与n +型浮动集电极2。此后，形成n +型Si外延生长层3。在这种情况下，p +沟道切割层5a和n +型浮动集电极2之间的距离应该与允许n +型Si层9保持在它们之间的距离宽，即使在n + 形成Si外延生长层3。此后，用CVD氮化膜7作为掩模形成隔离氧化膜4，并且n +型Si层9留在正在这种隔离氧化物的p +型沟道切割层5a的两端电影4。

83. 发明专利

JPS58184739A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS58184739A
公开(公告)日：1983-10-28
申请号：JP6778782
申请日：1982-04-22
申请人： Nec Corp
发明人： TAKADA TOSHIAKI
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762
CPC分类号： H01L21/7621
摘要： PURPOSE:To reduce bird beaks to encroach upon the element region of a semiconductor device by a method wherein after silicon at regions removed with an oxidation resistive coating is removed at proper depth, oxidation is performed to the inner sides from the coating pattern of the small coating using the small coating as the mask. CONSTITUTION:After an oxide film 32 and an oxidation resistive coating 33 are formed on a silicon substrate 31, thermal oxide films 34 and an oxide film 35 are formed. The oxide films 34, 35 are etched using a photo resist 36 smaller than the coating 33 as the mask, and the photo resist 36 is peeled off. The oxidation resistive coating 33 is etched using the remaining oxide film 35 as the mask, and selective oxidation is performed using the remaining coating 37 as the mask to form oxide films 38. When the selective oxide films are formed by this way, stress to be generated when second time oxidation is performed is mitigated, and the semiconductor device containing no crystal defect and having no reduction of carrier mobility can be offered.
摘要翻译：目的：通过以下方法减少鸟喙以侵入半导体器件的元件区域，其中在适当深度处除去具有氧化电阻涂层的区域中的硅之后，从小的涂层图案向内侧进行氧化使用小涂层作为掩模涂层。构成：在硅衬底31上形成氧化膜32和氧化电阻涂层33之后，形成热氧化膜34和氧化物膜35。使用小于作为掩模的涂层33的光致抗蚀剂36来蚀刻氧化物膜34,35，并且剥离光致抗蚀剂36。使用剩余的氧化膜35作为掩模来蚀刻氧化电阻涂层33，并且使用剩余的涂层37作为掩模进行选择性氧化以形成氧化膜38.当通过这种方式形成选择性氧化物膜时，应力为可以减轻第二时间氧化时产生的半导体器件，并且可以提供不含晶体缺陷并且不降低载流子迁移率的半导体器件。

84. 发明授权

US09478649B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09478649B2
公开(公告)日：2016-10-25
申请号：US15016258
申请日：2016-02-04
申请人： Changzhou ZhongMin Semi-Tech Co. Ltd.
发明人： Yuzhu Li
IPC分类号： H01L29/739 , H01L21/306 , H01L21/04 , H01L21/02 , H01L21/311 , H01L21/308 , H01L29/06 , H01L23/532 , H01L29/16 , H01L29/20 , H01L29/423 , H01L29/49 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7397 , H01L21/02164 , H01L21/0217 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/0475 , H01L21/30604 , H01L21/3081 , H01L21/3086 , H01L21/31111 , H01L21/7602 , H01L21/7621 , H01L23/53271 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/2003 , H01L29/4236 , H01L29/4916
摘要： A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer, N-drift layer and N-type CS layer within the N-drift layer near the top side. Multiple trench structures are formed by polysilicon core and gate oxide layer near the front side. There are active cells and plugged cells on top of the device. The polysilicon cores of the trenches in the active cells are connected to the gate electrode, and the polysilicon cores of the trenches in the plugged cells are connected to the emitter electrode. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and plugged cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in plugged cells are divided by N-drift layer, forming discontinuous P-type regions along the direction of trenches. And each P-well region in plugged cells is either electrically floating or connected to the emitter electrode.
摘要翻译：半导体器件包括：靠近顶侧的N漂移层内侧的金属集电体层，P型集电极层，N型场阻挡层，N漂移层和N型CS层。多个沟槽结构由靠近正面的多晶硅核心和栅极氧化物层形成。设备顶部有活动单元格和插入单元格。有源电池中的沟槽的多晶硅核心连接到栅电极，并且封装单元中的沟槽的多晶硅核心连接到发射极电极。有源电池中存在N +区和P +区，并通过绝缘层中的窗口连接到金属发射极层。活性细胞和封闭细胞中都有P阱区。活性电池中的P阱区是连续的，并通过P +区连接到发射极。堵塞单元中的P阱区域被N漂移层划分，沿沟槽方向形成不连续的P型区域。并且堵塞电池中的每个P阱区域电浮置或连接到发射极电极。

85. 发明申请

US20160240639A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160240639A1
公开(公告)日：2016-08-18
申请号：US15016258
申请日：2016-02-04
申请人： Changzhou ZhongMin Semi-Tech Co. Ltd.
发明人： Yuzhu Li
IPC分类号： H01L29/739 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7397 , H01L21/02164 , H01L21/0217 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/0475 , H01L21/30604 , H01L21/3081 , H01L21/3086 , H01L21/31111 , H01L21/7602 , H01L21/7621 , H01L23/53271 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/2003 , H01L29/4236 , H01L29/4916
摘要： A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer, N-drift layer and N-type CS layer within the N-drift layer near the top side. Multiple trench structures are formed by polysilicon core and gate oxide layer near the front side. There are active cells and plugged cells on top of the device. The polysilicon cores of the trenches in the active cells are connected to the gate electrode, and the polysilicon cores of the trenches in the plugged cells are connected to the emitter electrode. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and plugged cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in plugged cells are divided by N-drift layer, forming discontinuous P-type regions along the direction of trenches. And each P-well region in plugged cells is either electrically floating or connected to the emitter electrode.
摘要翻译：半导体器件包括：靠近顶侧的N漂移层内侧的金属集电体层，P型集电极层，N型场阻挡层，N漂移层和N型CS层。多个沟槽结构由靠近正面的多晶硅核心和栅极氧化物层形成。设备顶部有活动单元格和插入单元格。有源电池中的沟槽的多晶硅核心连接到栅电极，并且封装单元中的沟槽的多晶硅核心连接到发射极电极。有源电池中存在N +区和P +区，并通过绝缘层中的窗口连接到金属发射极层。活性细胞和封闭细胞中都有P阱区。活性电池中的P阱区是连续的，并通过P +区连接到发射极。堵塞单元中的P阱区域被N漂移层划分，沿沟槽方向形成不连续的P型区域。并且堵塞电池中的每个P阱区域电浮置或连接到发射极电极。

86. 发明申请

US20160233105A1 METHOD OF FORMING A TRENCH IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成TRENCH的方法
公开(公告)号：US20160233105A1
公开(公告)日：2016-08-11
申请号：US15016255
申请日：2016-02-04
申请人： Changzhou ZhongMin Semi-Tech Co. Ltd.
发明人： Yuzhu Li
IPC分类号： H01L21/306 , H01L21/308 , H01L21/311 , H01L21/04 , H01L21/02
CPC分类号： H01L29/7397 , H01L21/02164 , H01L21/0217 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/0475 , H01L21/30604 , H01L21/3081 , H01L21/3086 , H01L21/31111 , H01L21/7602 , H01L21/7621 , H01L23/53271 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/2003 , H01L29/4236 , H01L29/4916
摘要： A method to make a semiconductor device, a first SiO2 layer and a first Si3N4 layer are sequentially formed on the semiconductor substrate. The first SiO2 layer and the first Si3N4 layer are then patterned as etching mask to form a trench in a semiconductor substrate by a trench etching process. After this, a second SiO2 layer and a second Si3N4 layer are formed conformal onto the substrate. Anisotropic etching is then performed to remove the second Si3N4 and second SiO2 layer except on the trench sidewall. Then a thermal oxidation process is done to grow oxide only in trench bottom and at trench top corner. The radius of curvature of trench bottom and trench top corner is increased at the same time by this thermal oxidation process.
摘要翻译：在半导体衬底上依次形成制造半导体器件，第一SiO 2层和第一Si 3 N 4层的方法。然后将第一SiO 2层和第一Si 3 N 4层图案化为蚀刻掩模，以通过沟槽蚀刻工艺在半导体衬底中形成沟槽。此后，第二SiO 2层和第二Si 3 N 4层被共形形成在基板上。然后进行各向异性蚀刻以除去沟槽侧壁以外的第二Si 3 N 4和第二SiO 2层。然后进行热氧化工艺，仅在沟槽底部和沟槽顶角生长氧化物。通过该热氧化工艺，沟槽底部和沟槽顶角的曲率半径同时增加。

87. 发明申请

US20150255273A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150255273A1
公开(公告)日：2015-09-10
申请号：US14197858
申请日：2014-03-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： CHIA-CHUN MIAO , CHAO-WEN SHIH , SHIH-WEI LIANG , CHING-FENG YANG
IPC分类号： H01L21/02 , H01L21/762 , H01L21/66 , H01L21/78
CPC分类号： H01L21/7621 , H01L21/78 , H01L22/12 , H01L23/3178 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a die including a first surface, a recess extended from an aperture disposed on the first surface and including a sidewall disposed within the die, and a polymeric member configured for filling and sealing the recess and including a first outer surface and a second outer surface, wherein the first outer surface is interfaced with the sidewall of the recess.
摘要翻译：半导体结构包括：模具，其包括第一表面，从设置在第一表面上的孔延伸的凹部，并且包括设置在模具内的侧壁;以及聚合构件，构造成用于填充和密封凹部，并且包括第一外表面和第二外表面，其中第一外表面与凹槽的侧壁接合。

88. 发明授权

US09087869B2 Bulk semiconductor fins with self-aligned shallow trench isolation structures 有权
标题翻译：具有自对准浅沟槽隔离结构的散装半导体鳍片
公开(公告)号：US09087869B2
公开(公告)日：2015-07-21
申请号：US13900833
申请日：2013-05-23
申请人： International Business Machines Corporation
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/092 , H01L27/12 , H01L27/108 , H01L29/66 , H01L21/84 , H01L21/8238 , H01L21/762 , H01L29/06
CPC分类号： H01L21/7621 , H01L21/76205 , H01L21/76229 , H01L21/76232 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L27/10879 , H01L27/1211 , H01L29/0653 , H01L29/6653 , H01L29/66553 , H01L29/66787 , H01L29/66795 , H01L29/7851
摘要： A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.
摘要翻译：在具有外延取向的含硅衬底上依次形成硅 - 碳合金层和硅 - 锗合金层。通过使用图案化的硬掩模层作为蚀刻掩模并且硅 - 碳合金层作为蚀刻停止层的各向异性蚀刻在硅 - 锗合金层中形成沟槽。含硅半导体材料部分形成在每个沟槽的底表面和侧壁上，与硅 - 锗合金层和硅 - 碳合金层进行外延对准。去除硬掩模层和硅 - 锗合金层，并且在每个含鳍状半导体材料部分的侧壁上形成不透氧隔离物。物理暴露的半导体部分被转换成半导体氧化物部分，并且去除不透氧的间隔物。含鳍状半导体部分的剩余部分包括可用于形成半导体器件的半导体鳍片。

89. 发明授权

US07910495B2 Plasma oxidizing method, plasma processing apparatus, and storage medium 失效
标题翻译：等离子体氧化法，等离子体处理装置和储存介质
公开(公告)号：US07910495B2
公开(公告)日：2011-03-22
申请号：US12443589
申请日：2007-09-27
申请人： Toshihiko Shiozawa , Yoshiro Kabe , Takashi Kobayashi , Hikaru Adachi , Junichi Kitagawa , Nobuhiko Yamamoto
发明人： Toshihiko Shiozawa , Yoshiro Kabe , Takashi Kobayashi , Hikaru Adachi , Junichi Kitagawa , Nobuhiko Yamamoto
IPC分类号： H01L21/469
CPC分类号： H01L21/76229 , H01L21/02238 , H01L21/02252 , H01L21/31662 , H01L21/7621
摘要： A plasma oxidizing method includes a step of placing an object to be processed and having a surface containing silicon on a susceptor disposed in a processing vessel of a plasma processing apparatus, a step of producing a plasma from a processing gas containing oxygen in the processing vessel, a step of supplying high-frequency electric power to the susceptor and applying a high-frequency bias to the object to be processed when the plasma is produced, and a step of forming a silicon oxide film by oxidizing silicon in the surface of the object to be processed by the plasma.
摘要翻译：等离子体氧化方法包括将待处理物体放置在等离子体处理装置的处理容器中的基座上的步骤，在处理容器内从含有氧的处理气体生成等离子体的步骤向基座提供高频电力的步骤，在制造等离子体时向待处理物体施加高频偏压的步骤，以及通过在物体的表面氧化硅来形成氧化硅膜的步骤由等离子体处理。

90. 发明申请

US20100015815A1 PLASMA OXIDIZING METHOD, PLASMA PROCESSING APPARATUS, AND STORAGE MEDIUM 失效
标题翻译：等离子体氧化方法，等离子体处理装置和储存介质
公开(公告)号：US20100015815A1
公开(公告)日：2010-01-21
申请号：US12443589
申请日：2007-09-27
申请人： Toshihiko Shiozawa , Yoshiro Kabe , Takashi Kobayashi , Hikaru Adachi , Junichi Kitagawa , Nobuhiko Yamamoto
发明人： Toshihiko Shiozawa , Yoshiro Kabe , Takashi Kobayashi , Hikaru Adachi , Junichi Kitagawa , Nobuhiko Yamamoto
IPC分类号： H01L21/31
CPC分类号： H01L21/76229 , H01L21/02238 , H01L21/02252 , H01L21/31662 , H01L21/7621
摘要： A plasma oxidizing method includes a step of placing an object to be processed and having a surface containing silicon on a susceptor disposed in a processing vessel of a plasma processing apparatus, a step of producing a plasma from a processing gas containing oxygen in the processing vessel, a step of supplying high-frequency electric power to the susceptor and applying a high-frequency bias to the object to be processed when the plasma is produced, and a step of forming a silicon oxide film by oxidizing silicon in the surface of the object to be processed by the plasma.
摘要翻译：等离子体氧化方法包括将待处理物体放置在等离子体处理装置的处理容器中的基座上的步骤，在处理容器内从含有氧的处理气体生成等离子体的步骤向基座提供高频电力的步骤，在制造等离子体时向待处理物体施加高频偏压的步骤，以及通过在物体的表面氧化硅来形成氧化硅膜的步骤由等离子体处理。

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