专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

EP1019959B1 INTERCONNECT STRUCTURE WITH A LOW PERMITTIVITY DIELECTRIC LAYER 失效
标题翻译： LEITERBAHNSTRUKTUR MIT EINEM DIELEKTRIKUM MIT EINER NIEDRIGENPERMITIVITÄT
公开(公告)号：EP1019959B1
公开(公告)日：2003-02-12
申请号：EP98913232.9
申请日：1998-03-27
申请人： ADVANCED MICRO DEVICES INC.
发明人： MAY, Charles , CHEUNG, Robin
IPC分类号： H01L21/768 , H01L21/3105
CPC分类号： H01L21/02126 , H01L21/02134 , H01L21/31053 , H01L21/3121 , H01L21/31629 , H01L21/76819 , H01L23/5329 , H01L2924/0002 , Y10S438/906 , H01L2924/00
摘要： A method of making a semiconductor device includes forming a low permittivity dielectric layer over one or more conductive lines of a semiconductor device. The dielectric layer is made using a silicon-containing material having a relatively low permittivity including, for example, silicon oxyfluoride (SiOyFx) and hydrogen silsesquioxane (HSQ). An optional oxide layer may be formed over the dielectric layer. At least a portion of the dielectric layer and/or the optional oxide layer is subsequently removed to form a planar dielectric layer having a contaminated surface layer. The contaminated surface layer is due to exposure to water and is removed by, for example, exposing the surface to an acid, such as hydrofluoric acid.
摘要翻译：制造半导体器件的方法包括在半导体器件的一个或多个导电线上形成低介电常数介电层。电介质层使用包含例如氟氧化硅（SiO yF x）和氢倍半硅氧烷（HSQ））的具有较低介电常数的含硅材料制成。可以在电介质层上形成任选的氧化物层。随后去除介电层和/或任选的氧化物层的至少一部分以形成具有污染表面层的平面介电层。受污染的表面层是由于暴露在水中而被除去，例如通过将表面暴露于酸如氢氟酸。

82. 发明公开

EP1264329A2 PLASMA DEPOSITION METHOD AND SYSTEM 有权
标题翻译：方法和装置等离子涂层
公开(公告)号：EP1264329A2
公开(公告)日：2002-12-11
申请号：EP01912463.5
申请日：2001-03-16
申请人： Tokyo Electron Limited
发明人： AKAHORI, Takashi,Tokyo Electron AT Limited
IPC分类号： H01J37/32 , H01L21/316 , C23C16/40
CPC分类号： H01J37/32082 , C23C16/401 , C23C16/5096 , H01J37/32165 , H01L21/02126 , H01L21/02131 , H01L21/0214 , H01L21/02211 , H01L21/02274 , H01L21/31629 , H01L21/31633
摘要： There is provided a deposition technique wherein the amounts of eliminated F and H are small in the deposition of an insulating film, such as an SiOF film or an SiCHO film, which contains silicon, oxygen and other components and which has a lower dielectric constant than the dielectric constant of a silicon oxide film. A plasma processing system for producing plasma with the energy of a power applied between first and second electrodes which are provided in a vacuum vessel so as to face each other in parallel and which are connected to separate high-frequency power supplies, respectively, is used. An object to be processed, e.g., a semiconductor wafer is mounted on the first electrode. The frequency of the high-frequency power applied to the first electrode is set to be in the range of from 2 MHz to 9 MHz, and the frequency of the high-frequency power applied to the second electrode is set to be 50 MHz or higher, to deposit an insulating film on the wafer.

83. 发明公开

EP1225194A2 Method of forming a dielectric interlayer film with organosilicon precursors 有权
标题翻译：一种生产有机硅使用的前体的层间绝缘层的过程
公开(公告)号：EP1225194A2
公开(公告)日：2002-07-24
申请号：EP02001014.6
申请日：2002-01-17
申请人： AIR PRODUCTS AND CHEMICALS, INC.
发明人： Vincent, Jean Louise , O'Neill, Mark Leonard , Withers, Howard Paul, Jr. , Beck, Scott Edward , Vrtis, Raymond Nicholas
IPC分类号： C08G77/04 , C23C16/40 , H01L21/316
CPC分类号： C09D183/06 , B05D1/60 , C23C16/401 , H01L21/02126 , H01L21/02131 , H01L21/02216 , H01L21/02274 , H01L21/3121 , H01L21/31629 , H01L21/31633
摘要： A method of forming a low dielectric constant interlayer dielectric film on a substrate by reacting, under chemical vapor deposition conditions sufficient to deposit the film on the substrate, an organosilicon precursor comprising a silyl ether, a silyl ether oligomer, or an organosilicon compound containing one or more reactive groups, to form an interlayer dielectric film having a dielectric constant of 3.5 or less. The films formed by the above method.
摘要翻译：形成低介电常数层间的方法，电介质薄膜上的基材通过使足以在基片上沉积薄膜的化学气相沉积条件下，以有机硅前体，其包括甲硅烷基醚，甲硅烷醚低聚物，或在有机硅化合物含有一个或多个反应性基团，以形成层间绝缘膜，具有3.5或更小的介电常数。由上述方法形成的膜。

84. 发明授权

EP0761841B1 Method for forming film 失效
标题翻译：一种用于生产层的方法
公开(公告)号：EP0761841B1
公开(公告)日：2002-06-12
申请号：EP96112891.5
申请日：1996-08-09
申请人： CANON SALES CO., INC. , SEMICONDUCTOR PROCESS LABORATORY CO., LTD.
发明人： Maeda, Kazuo, Semiconductor Process Lab Co., Ltd. , Tokumasu, N., Semiconductor Process Lab Co., Ltd. , Yuyama, Yoshiaki
IPC分类号： C23C16/40 , C23C16/30 , H01L21/00 , C23C16/56
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02271 , H01L21/0234 , H01L21/31629

85. 发明公开

EP1156134A2 Method and apparatus of depositing a layer of nitrogen-doped fluorinated silicate glass 审中-公开
标题翻译：用于沉积氟硅玻璃层的方法和装置掺杂氮
公开(公告)号：EP1156134A2
公开(公告)日：2001-11-21
申请号：EP01111449.3
申请日：2001-05-10
申请人： APPLIED MATERIALS, INC.
发明人： Zhang, Lin , Li, Zhuang , Ma, Wen
IPC分类号： C23C16/42
CPC分类号： H01L21/02131 , C23C16/401 , C23C16/507 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/3143 , H01L21/31629 , Y10S438/958
摘要： Gap-fill and damascene methods are disclosed for depositing an insulating thin film of nitrofluorinated silicate glass on a substrate in a process chamber. A high-density plasma, generated from a gaseous mixture of silicon-, fluorine-, oxygen-, and nitrogen-containing gases, deposits a layer of nitrofluorinated silicate glass onto the substrate. For gap-fill applications, the substrate is biased with a bias power density between 4.8 and 11.2 W/cm 2 and the ratio of flow rate for the oxygen-containing gas to the combined flow rate for all silicon-containing gases in the process chamber is between 1.0 and 1.8, preferably between 1.2 and 1.4. For damascene applications, the bias power density is less than 3.2 W/cm 2 , preferably 1.6W/cm 2 , and the flow rate ratio is between 1.2 and 3.0. Using optimized parameters, the thin film has a lower dielectric constant and better adhesion properties than fluorosilicate glass.

86. 发明公开

EP1094508A2 Void-free low K dielectric composite layer between metal lines in integrated circuit structure 审中-公开
标题翻译：与用于集成电路的结构的低介电常数无气泡的复合电介质层
公开(公告)号：EP1094508A2
公开(公告)日：2001-04-25
申请号：EP00122684.4
申请日：2000-10-18
申请人： LSI LOGIC CORPORATION
发明人： Catabay, Wilbur G. , Schinella, Richard
IPC分类号： H01L21/316
CPC分类号： H01L21/02126 , H01L21/02131 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/3146 , H01L21/31629 , H01L21/76801
摘要： A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer. A second layer of low k silicon oxide dielectric material, having a faster deposition rate than the first layer, is then deposited over the first layer up to the desired overall thickness of the low k silicon oxide dielectric layer. In a preferred embodiment, the steps to form the resulting composite layer of low k silicon oxide dielectric material are all carried out in a single vacuum processing apparatus without removal of the substrate from the vacuum apparatus.
摘要翻译：的低k氧化硅电介质材料制成的复合层是在上一集成电路结构的其上具有紧密间隔开的金属线的半导体基板上形成氧化物层。的低k氧化硅介电材料的复合层表现出的沉积速率的紧密间隔开的金属线之间的高纵横比的区域，无空隙的沉积性质在与标准氧化k硅片，并且经由中毒特性降低等地区。的低k氧化硅介电材料的复合层是由在高纵横比的区域上沉积FORMED之间紧密间隔开的金属线路，低介电常数的氧化硅介电材料的参展无空隙沉积性质直到低k的所得到的沉积的第一层氧化硅的介电材料到达所述氧化物层上的金属线的顶部的水平。的低k氧化硅的介电材料的第二层，具有更快的沉积速率比第一层，然后在所述第一层到所述的低k氧化硅电介质层的所需总厚度沉积。在一个优选的实施方案中，步骤以形成的低k氧化硅的介电材料的所得复合层在单一的真空处理装置都被进行，而不去除所述真空装置用基板。

87. 发明公开

EP1081249A1 Method for depositing fluorinated silica glass layers 审中-公开
标题翻译： Verfahren zum Auftragen fluorierter Silikaglas-Schichten
公开(公告)号：EP1081249A1
公开(公告)日：2001-03-07
申请号：EP00119011.5
申请日：2000-09-01
申请人： Applied Materials, Inc.
发明人： M'Saad, Hichem , Tribula, Dana , Vellaikal, Manoj , Desai, Sameer , Moghadam, Farhad
IPC分类号： C23C16/40 , C23C16/50 , H01L21/316
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31629
摘要： A method of formation of a damascene FSG film with good adhesion to silicon nitride in an HDP-CVD system. Silane (SiH 4 ), silicon tetrafluoride (SiF 4 ), oxygen (O 2 ) and argon (Ar) are used as the reactant gases. SiH 4 , SiF 4 , and O 2 react to form the FSG. Ar is introduced to promote gas dissociation. All four gases are used for depositing most of the FSG film. SiH 4 is not used during deposition of the interfacial part of the FSG film. The interfacial part of the FSG film refers either to the topmost portion, if silicon nitride is to be deposited on top of the FSG or the bottom portion if the FSG is to be deposited on top of silicon nitride. Using SiH 4 with the SiF 4 tends to mitigate the destructive effects of SiF 4 throughout most of the deposition. By removing the SiH 4 from the deposition of the interfacial part of the FSG film less hydrogen is incorporated into the film in the interfacial region and adhesion to overlying or underlying silicon nitride is improved.
摘要翻译：在HDP-CVD系统中形成对氮化硅具有良好粘附性的镶嵌FSG膜的方法。硅烷（SiH4），四氟化硅（SiF4），氧（O2）和氩（Ar）用作反应气体。 SiH4，SiF4和O2反应形成FSG。引入Ar来促进气体分解。所有四种气体都用于沉积大部分FSG膜。在沉积FSG膜的界面部分期间不使用SiH4。如果将FSG沉积在氮化硅的顶部，则FSG膜的界面部分指的是最高部分，如果氮化硅沉积在FSG或底部的顶部。 SiF4与SiF4一起使用可以减轻SiF4在大部分沉积过程中的破坏作用。通过从FSG膜的界面部分的沉积中除去SiH 4，在界面区域中更少的氢被引入到膜中，并且改善了覆盖或下层氮化硅的粘附性。

88. 发明公开

EP1050599A3 Method of forming interlayer insulating film 失效
标题翻译： Verfahren zum Herstellen eines isolierenden Zwischenfilms
公开(公告)号：EP1050599A3
公开(公告)日：2000-12-13
申请号：EP00117095.0
申请日：1997-08-29
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Sugahara, Gaku , Aoi, Nobuo , Arai, Koji , Sawada, Kazuyuki
IPC分类号： C23C16/40 , C23C16/26 , C23C16/30 , H01L21/314 , H01L21/316
CPC分类号： H01L21/02126 , C23C16/26 , C23C16/30 , C23C16/401 , H01L21/0212 , H01L21/02131 , H01L21/02205 , H01L21/02211 , H01L21/02214 , H01L21/02216 , H01L21/02274 , H01L21/31051 , H01L21/31058 , H01L21/3122 , H01L21/3127 , H01L21/314 , H01L21/31608 , H01L21/31612 , H01L21/31629 , H01L21/31633 , H01L21/76801 , H01L21/76807
摘要： The invention relates to a material containing, as a main component, a gas mixture of an organic silicon compound represented by the following general formula:R 1 x Si(OR 2 ) 4-x (wherein R 1 is a phenyl group; R 2 is an alkyl group; and x is an integer of 1 to 3) or of a siloxane derivative and a flourinated carbon compound is caused to undergo plasma polymerization or react with an oxidizing agent to form an interlayer insulating film composed of a silicon oxide film containing an organic component.
摘要翻译：本发明涉及以下通式表示的有机硅化合物的气体混合物作为主要成分的材料：R 1 x Si（OR 2）4-x（其中R 1为苯基; R 2为烷基，x为1〜3的整数）或硅氧烷衍生物和增溶的碳化合物进行等离子体聚合或与氧化剂反应形成层间绝缘膜由含有有机成分的氧化硅膜构成。

89. 发明公开

EP0975017A2 Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication 审中-公开
标题翻译：硅氧烷基硝基氟化物氟化物玻璃纤维
公开(公告)号：EP0975017A2
公开(公告)日：2000-01-26
申请号：EP99113533.6
申请日：1999-07-06
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Lee, Gill Yong
IPC分类号： H01L21/314
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/3145 , H01L21/31629 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/3192 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor device and method of forming a patterned conductive layer on a semiconductor substrate are provided so as to prevent fluorine substance outflow from a fluorinated silicate glass (FSG) layer thereon and simultaneously so as to suppress back reflection of light waves into a photoresist layer during photolithographic processing. The substrate is coated in turn with a conductive layer, a dielectric (e.g., silicon dioxide) liner, a FSG layer, a silicon oxynitride layer preventing fluorine substance outflow therethrough from the FSG layer and also forming an antireflective coating (ARC), and a photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the underlying silicon oxynitride layer. The uncovered pattern portions of the silicon oxynitride ARC layer and corresponding underlying portions of the FSG layer and dielectric liner are then removed, e.g., by,a single dry etching step, to expose pattern portions of the conductive layer for metallization. Upon metallization, the substrate is provided with a combination of the FSG layer and silicon oxynitride layer, in which the silicon oxynitride layer prevents fluorine substance outflow therethrough from the underlying FSG layer to an overlying conductive layer.
摘要翻译：提供半导体器件和在半导体衬底上形成图案化导电层的方法，以防止氟物质从其上的氟化硅酸盐玻璃（FSG）层流出，并同时抑制光波反射到光致抗蚀剂层中光刻处理。依次用导电层，电介质（例如，二氧化硅）衬垫，FSG层，氮氧化硅层涂覆衬底，防止氟物质从FSG层流出并形成抗反射涂层（ARC），以及光致抗蚀剂层。光致抗蚀剂层被曝光和显影以露出下面的氮氧化硅层的图案部分。氧氮化硅ARC层的未覆盖图案部分和FSG层和电介质衬垫的相应的下面部分然后例如通过单次干蚀刻步骤被去除，以暴露用于金属化的导电层的图案部分。在金属化时，基板设置有FSG层和氮氧化硅层的组合，其中氧氮化硅层防止氟物质从下面的FSG层流出到覆盖的导电层。

90. 发明公开

EP0932188A3 Glass formation on a semi-conductor wafer 有权
标题翻译：在半导体晶片上沉积玻璃
公开(公告)号：EP0932188A3
公开(公告)日：1999-11-17
申请号：EP98310017.3
申请日：1998-12-07
申请人： International Business Machines Corporation , SIEMENS AKTIENGESELLSCHAFT , LAM RESEARCH CORPORATION
发明人： Kirchhof, Markus , Chakravarti, Ashima , Ilg, Matthias , McKinley, Kevin A. , Nguyen, Son V. , Shapiro, Michael J.
IPC分类号： H01L21/316 , H01L21/3105
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02131 , H01L21/02211 , H01L21/31625 , H01L21/31629
摘要： An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. Preferably the glass deposition is performed at a temperature of about 750-850°C and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式