专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明公开

US20230301052A1 DATA BACKUP UNIT FOR STATIC RANDOM-ACCESS MEMORY DEVICE 审中-公开
公开(公告)号：US20230301052A1
公开(公告)日：2023-09-21
申请号：US17694974
申请日：2022-03-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yun-Feng Kao , Katherine H. Chiang
IPC分类号： H01L27/11 , G11C14/00 , H01L27/1159 , H01L27/11592 , H01L21/28 , H01L29/51 , G11C5/06
CPC分类号： H01L27/1116 , G11C14/0072 , H01L27/1104 , H01L27/1159 , H01L27/11592 , H01L29/40111 , H01L29/516 , G11C5/063 , H01L29/41775
摘要： Various embodiments of the present application are directed towards a memory device including a memory cell. The memory cell includes a plurality of semiconductor devices disposed on a substrate. A lower inter-metal dielectric (IMD) structure overlies the semiconductor devices. A plurality of conductive vias and a plurality of conductive wires are disposed within the IMD structure and are electrically coupled to the semiconductor devices. A data backup unit overlies the plurality of conductive vias and wires. The data backup unit includes a first source/drain structure, a second source/drain structure, a channel layer, a first memory gate structure, and a second memory gate structure. The first and second memory gate structures include an upper gate electrode over a ferroelectric layer. The first and second source/drain structures are directly electrically coupled to the semiconductor devices by way of the conductive vias and wires.

82. 发明申请

US20190244666A1 METHODS AND APPARATUS FOR MEMORY CELLS THAT COMBINE STATIC RAM AND NON VOLATILE MEMORY 审中-公开
公开(公告)号：US20190244666A1
公开(公告)日：2019-08-08
申请号：US16265810
申请日：2019-02-01
申请人： Fu-Chang Hsu
发明人： Fu-Chang Hsu
IPC分类号： G11C14/00
CPC分类号： G11C14/0072 , G11C11/412 , G11C11/419 , G11C14/0081 , G11C14/009
摘要： Methods and apparatus for memory cells that combine static random-access memory and non-volatile memory. In an exemplary embodiment, a memory cell is provided that includes a static random-access memory (SRAM) cell having Q and QB nodes and a non-volatile memory (NVM) array having a plurality of NVM cells. Each NVM cell comprises a memory element and a selector. The memory cell also includes select gates that selectively couple at least one of the Q and QB nodes to the plurality of NVM cells.

83. 发明申请

US20190172539A1 POLARIZATION-BASED CONFIGURABLE LOGIC GATE 审中-公开
公开(公告)号：US20190172539A1
公开(公告)日：2019-06-06
申请号：US15829076
申请日：2017-12-01
申请人： NaMLab gGmbH
发明人： Stefan Slesazeck , Halid Mulaosmanovic , Evelyn Breyer
IPC分类号： G11C14/00 , G11C13/00 , H01L21/28 , H01L27/10 , H01L27/11507
CPC分类号： G11C14/0072 , G11C7/1006 , G11C11/223 , G11C11/2259 , G11C11/5657 , G11C13/0004 , G11C14/009 , H01L27/101 , H01L27/11507 , H01L29/40111 , H03K19/0944
摘要： A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.

84. 发明申请

US20180122478A1 FERROELECTRIC BASED MEMORY CELL WITH NON-VOLATILE RETENTION 审中-公开
公开(公告)号：US20180122478A1
公开(公告)日：2018-05-03
申请号：US15567942
申请日：2015-05-28
申请人： Intel Corporation
发明人： Daniel H. MORRIS , Uygar E. AVCI , Ian A. YOUNG
IPC分类号： G11C14/00 , G11C11/22 , H01L27/11502
CPC分类号： G11C14/0072 , G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C14/0027 , H01L27/11502
摘要： Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.

85. 发明申请

US20180108414A1 DATA HOLDING DEVICE, NONVOLATILE DATA HOLDING DEVICE, AND DATA READING METHOD 审中-公开
公开(公告)号：US20180108414A1
公开(公告)日：2018-04-19
申请号：US15722501
申请日：2017-10-02
申请人： Rohm Co., Ltd.
发明人： Hiromitsu Kimura , Takanori Ozawa
IPC分类号： G11C14/00 , G11C11/56 , G11C11/22 , H03K19/0185 , H03K19/0948 , H02M3/07
CPC分类号： G11C14/0072 , G11C7/065 , G11C11/221 , G11C11/2273 , G11C11/5657 , G11C2013/0042 , H02M3/07 , H03K19/018521 , H03K19/09485
摘要： A data holding device 100 has an inverter loop 101, a differential pair circuit 102 connected to the ground terminals of inverters, a first potential setter 103 configured to turn the output terminals of the inverters to a first potential (VDD), and a second potential setter 104 configured to turn the ground terminals of the inverters to a second potential (VSS). During data holding, the differential pair circuit 102 and the first potential setter 103 are disabled so that the ground terminals of the inverters are at the second potential. During data writing, the differential pair circuit 102 is disabled so that the output terminal of one inverter is at the first potential and the ground terminal of the other inverter is at the second potential.

86. 发明授权

US09412448B2 C-element with non-volatile back-up 有权
标题翻译：具有非易失性备份的C元素
公开(公告)号：US09412448B2
公开(公告)日：2016-08-09
申请号：US14845213
申请日：2015-09-03
申请人： Commissariat à{grave over ( )}l'énergie atomique et aux énergies alternatives , Centre National de la Recherche Scientifique
发明人： Grégory Di Pendina , Edith Beigne , Eldar Zianbetov
IPC分类号： G11C14/00 , G11C13/00 , G11C11/14 , H03K19/017 , H03K19/0185 , H03K19/20 , G11C11/16 , G11C11/22
CPC分类号： G11C13/0069 , G11C11/14 , G11C11/1675 , G11C11/22 , G11C11/2275 , G11C13/0004 , G11C14/0072 , G11C14/0081 , G11C14/009 , H03K19/01707 , H03K19/018585 , H03K19/20
摘要： The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes (Q, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element (202) having a first terminal coupled to the first storage node (Q); a second resistive element (204) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (Rmin, Rmax), wherein a second terminal of the first resistive element (202) is coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232).
摘要翻译：本发明涉及一种电路，包括：具有第一和第二输入节点的C元件和交叉耦合在第一和第二互补存储节点（Q，Z）之间的第一和第二反相器（110,112），第二存储节点（Z）形成C元件的输出节点; 和非易失性存储器，包括：具有耦合到所述第一存储节点（Q）的第一端子的第一电阻元件（202）。具有耦合到第二存储节点（Z）的第一端子的第二电阻元件（204），所述第一和第二电阻元件中的至少一个可编程为具有至少两个电阻状态（Rmin，Rmax）中的至少一个，其中a 第一电阻元件（202）的第二端子经由第一晶体管（210）耦合到第二电阻元件（204）的第二端子; 和控制电路（232）。

87. 发明申请

US20160172036A1 MEMORY CELL WITH RETENTION USING RESISTIVE MEMORY 审中-公开
标题翻译：使用电阻记忆的记忆单元
公开(公告)号：US20160172036A1
公开(公告)日：2016-06-16
申请号：US14129676
申请日：2013-08-16
申请人： Charles AUGUSTINE , Carlos TOKUNAGA , James W. TSCHANZ
发明人： Charles AUGUSTINE , Carlos TOKUNAGA , James W. TSCHANZ
IPC分类号： G11C14/00 , G11C11/16
CPC分类号： G11C14/0081 , G11C11/1697 , G11C13/0011 , G11C14/0072 , G11C14/009
摘要： Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: a memory element including cross-coupled cells having a first node and a second node; a first transistor coupled to the first node; a second transistor coupled to the second node; and a resistive memory element coupled to the first and second transistors.
摘要翻译：描述了一种包括使用电阻性存储器保持的存储单元的装置。该装置包括：存储元件，其包括具有第一节点和第二节点的交叉耦合小区; 耦合到所述第一节点的第一晶体管; 耦合到所述第二节点的第二晶体管; 以及耦合到第一和第二晶体管的电阻性存储元件。

88. 发明申请

US20160111138A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20160111138A1
公开(公告)日：2016-04-21
申请号：US14725102
申请日：2015-05-29
申请人： Rohm Co., Ltd.
发明人： Shintaro IZUMI , Tomoki NAKAGAWA , Hiroshi KAWAGUCHI , Masahiko YOSHIMOTO
IPC分类号： G11C11/22 , G11C29/08
CPC分类号： G11C14/0072 , G11C11/221 , G11C11/2259 , G11C29/08 , G11C29/50
摘要： Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.
摘要翻译：作为配置，铁电阴影存储器的控制方法和测试方法，提出以下步骤：（1）在读/写操作期间不执行位线预充电的位线非预充电方法; （2）平板线电荷共享方法，其中在存储/调用操作期间顺序驱动的板线之间共享电荷; （3）在写入操作期间字线上的电位升高的字线升压方法; （4）一种板线驱动器升压方法，其中在行存储/调用操作期间升高板式驱动器的驱动能力; 以及（5）通过从芯片外部任意设定位线上的电位来检测铁电电容器的缺陷的测试方法。

89. 发明申请

US20160064077A1 MEMORY CELL WITH NON-VOLATILE DATA STORAGE 有权
标题翻译：具有非易失性数据存储的存储单元
公开(公告)号：US20160064077A1
公开(公告)日：2016-03-03
申请号：US14784871
申请日：2014-04-15
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
发明人： Gregory Di Pendina
IPC分类号： G11C13/00 , G11C11/16 , G11C11/22
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1675 , G11C11/2275 , G11C13/0002 , G11C13/0004 , G11C14/0072 , G11C14/0081 , G11C14/009
摘要： The invention concerns a memory cell comprising first and second resistive elements (202, 204) coupled respectively between first and second storage nodes and first and second intermediate nodes, at least one of them being programmable to take up one of at least two resistive states (Rmin′ Rmax); a third transistor (220) coupled between the first and second intermediate nodes; a fourth transistor (502) coupled between the first storage node (206, 210) and a data input node (506); and a control circuit arranged, during a write phase, to activate the third and fourth transistors and to couple the data input node to a second supply voltage (VDD, GND) via a first circuit block (508) in order to generate a current in a first direction through the first and second resistive elements in order to programme the resistive state of at least one of the elements.
摘要翻译：本发明涉及包括分别耦合在第一和第二存储节点与第一和第二中间节点之间的第一和第二电阻元件（202,204）的存储单元，其中的至少一个可编程为占据至少两个电阻状态（ Rmin'Rmax）; 耦合在所述第一和第二中间节点之间的第三晶体管（220）耦合在第一存储节点（206,210）和数据输入节点（506）之间的第四晶体管（502）; 以及控制电路，在写入阶段期间布置以激活第三和第四晶体管，并且经由第一电路块（508）将数据输入节点耦合到第二电源电压（VDD，GND），以便产生电流通过第一和第二电阻元件的第一方向，以便对至少一个元件的电阻状态进行编程。

90. 发明授权

US08854858B2 Signal level conversion in nonvolatile bitcell array 有权
标题翻译：非易失性位单元阵列中的信号电平转换
公开(公告)号：US08854858B2
公开(公告)日：2014-10-07
申请号：US13753819
申请日：2013-01-30
申请人： Texas Instruments Incorporated
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G11C11/22 , H03K3/02
CPC分类号： H03K3/02 , G11C11/2275 , G11C11/419 , G11C14/0072 , H03K3/356104
摘要： A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.
摘要翻译：片上系统（SoC）包括配置为在较低电源电压下操作的一个或多个核心逻辑块和配置为在较高电源电压下工作的存储器阵列。存储器中的每个位单元具有串联连接在第一板线和第二板线之间以形成节点Q的两个铁电电容器。通过激活写驱动器将数据位电压传送到节点Q以提供数据位电压响应到较低的电源电压。通过激活耦合到所选位单元的节点Q的读出放大器，在节点Q上升高数据位电压，使得感测放大器感测节点Q上的数据位电压，并且响应于增加节点上的数据位电压 Q到更高的电源电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式