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81. 发明申请

WO2006127408A3 METHOD AND SYSTEM FOR INCREASED ACCURACY FOR EXTRACTION OF ELECTRICAL PARAMETERS 审中-公开
标题翻译：用于提取电气参数的提高精度的方法和系统
公开(公告)号：WO2006127408A3
公开(公告)日：2007-03-15
申请号：PCT/US2006019304
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS INC , SCHEFFER LOUIS K , STAUD WOLFGANG H , HUCKABAY JUDY
发明人： SCHEFFER LOUIS K , STAUD WOLFGANG H , HUCKABAY JUDY
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An improved method, system, and computer program product is disclosed for increased accuracy for extraction of electrical parameters of an IC design. Extraction is performed upon the expected geometric model of the printed layout once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for performing extraction since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The extracted electrical parameters are checked for acceptability. If not acceptable, then the IC design can be modified to address any identified problems or desired improvements to the design.
摘要翻译：公开了一种改进的方法，系统和计算机程序产品，用于提高IC设计的电参数的精度。一旦制造和平版印刷过程效果被考虑，就按照打印布局的预期几何模型进行提取。这提供了一种更精确的执行提取方法，因为它是被分析的实际预期几何形状，而不是不能准确对应于实际制造的IC产品的理想化模型。检查提取的电气参数是否可接受。如果不能接受，则可以修改IC设计以解决任何已识别的问题或对设计的期望改进。

82. 发明申请

WO2006127409A2 SYSTEM AND METHOD FOR STATISTICAL DESIGN RULE CHECKING 审中-公开
标题翻译：统计设计规则检查系统与方法
公开(公告)号：WO2006127409A2
公开(公告)日：2006-11-30
申请号：PCT/US2006/019305
申请日：2006-05-19
申请人： CADENCE DESIGN SYSTEMS, INC. , SCHEFFER, Louis K.
发明人： SCHEFFER, Louis K.
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules. Probability information is compiled for each circuit component, that specifies the probability of the circuit component working if a characteristic of the circuit component is varied. As the design rules are examined, the probability of each component working is calculated. The probabilities are combined to determine the overall probability of success for the IC design. Furthermore, the IC design may be broken into a plurality of portions, and design rules can be separately specified for each portion. This allows a designer the flexibility to use different design rules on different portions of the IC design.
摘要翻译：允许集成电路设计者指定一个或多个设计规则的方法和系统，并且基于设计规则确定IC设计成功的预期概率。针对每个电路组件编制概率信息，其指定电路组件的特性如果变化时电路组件工作的概率。随着设计规则的检验，每个部件工作的概率被计算出来。将概率相结合以确定IC设计的成功概率。此外，IC设计可以被分成多个部分，并且可以为每个部分分别指定设计规则。这允许设计人员灵活地在IC设计的不同部分使用不同的设计规则。

83. 发明申请

WO2005122028A2 LOCAL PREFERRED DIRECTION ARCHITECTURE, TOOLS, AND APPARATUS 审中-公开
标题翻译：本地优选方向架构，工具和装置
公开(公告)号：WO2005122028A2
公开(公告)日：2005-12-22
申请号：PCT/US2005/019361
申请日：2005-06-04
申请人： CADENCE DESIGN SYSTEMS, INC , HETZEL, Asmus , MALHOTRA, Anish , FUJIMURA, Akira , JACQUES, Etienne , FRANKLE, Jon , HARRISON, David, S. , FEATHER, Heath , MATVEEV, Alexandre , KING, Roger
发明人： HETZEL, Asmus , MALHOTRA, Anish , FUJIMURA, Akira , JACQUES, Etienne , FRANKLE, Jon , HARRISON, David, S. , FEATHER, Heath , MATVEEV, Alexandre , KING, Roger
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout.
摘要翻译：本发明的一些实施例提供了与一个或多个EDA工具（例如放置，布线等）一起使用的局部优选方向（LPD）布线模型。 LPD布线模型允许至少一个布线层具有各自具有与特定布线层不同的优选方向的一组区域。此外，每个区域具有局部优选方向，其不同于该组中至少一个其它区域的局部优选方向。此外，至少两个区域具有两个不同的多边形形状，并且该集合中的区域不包含该组中的另一区域。一些实施例还提供了一种图形用户界面（GUI），其便于LPD设计布局的视觉呈现，并提供在设计布局中创建和操纵LPD区域的工具。

84. 发明申请

WO2005122027A2 LOCAL PREFERRED DIRECTION ROUTING AND LAYOUT GENERATION 审中-公开
标题翻译：本地优选方向路由和布局生成
公开(公告)号：WO2005122027A2
公开(公告)日：2005-12-22
申请号：PCT/US2005/019359
申请日：2005-06-04
申请人： CADENCE DESIGN SYSTEMS, INC. , HETZEL, Asmus , MALHOTRA, Anish , CHERUKURI, Deepak , JACQUES, Etienne , FRANKLE, Jon
发明人： HETZEL, Asmus , MALHOTRA, Anish , CHERUKURI, Deepak , JACQUES, Etienne , FRANKLE, Jon
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Some embodiments of the invention provide a method for defining routes in a design layout. The method defines at least one particular wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring directions to define a detailed route on the wiring layer. In some embodiments, the method defines a first route that traverse first and second regions between two layers by using a first via that has a first pad in the second region. The method also defines a second route that traverses the second region and a third region in the two layers by using a second via that has a second pad in the second region, where the first and second pads have different shapes.
摘要翻译：本发明的一些实施例提供了一种用于在设计布局中定义路线的方法。该方法限定了至少一个具有不同局部优选布线方向的至少两个区域的特定布线层。然后，该方法使用不同的局部优选布线方向来在布线层上限定详细路线。在一些实施例中，该方法通过使用在第二区域中具有第一焊盘的第一通孔限定穿过两层之间的第一和第二区域的第一路由。该方法还通过使用在第二区域中具有第二焊盘的第二通孔来定义穿过第二区域的第二区域和第二区域中的第三区域，其中第一和第二焊盘具有不同的形状。

85. 发明申请

WO2004102630A2 TWO-STAGE CLOCK TREE SYNTHESIS 审中-公开
标题翻译：两阶段时钟合成
公开(公告)号：WO2004102630A2
公开(公告)日：2004-11-25
申请号：PCT/US2004/014676
申请日：2004-05-10
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： TSAO, Chung-wen , TENG, Chin-Chi
IPC分类号： H01L
CPC分类号： G06F17/5045 , G06F1/10
摘要： A clock tree synthesis (CTS) tool determines how to position a hierarchy of buffers for fanning out a clock signal to clocked devices ("sinks") within an integrated circuit (IC). The tool first clusterizes the sinks and places a lowest level fan-out buffer near each cluster. The tool then iteratively places progressively higher level buffers by clusterizing a last-placed buffer level and then placing a next higher level buffer near the centroid of each lower level buffer cluster, until the tool has placed buffers at a mid-level for which variation in path distances between that level and a next higher buffer level exceeds a predetermined limit. The CTS tool then places a top level buffer at the centroid of the mid-level buffers, divides the layout into partitions, each containing a similar number of mid-level buffers, and then places a second-highest level buffer in each partition. The CTS iteratively places each next lower buffer level by dividing each partition into progressively smaller partitions and placing progressively lower level buffers in each smaller partition until it places buffers at a level having sufficient number of buffers to drive the mid-level buffers.
摘要翻译：时钟树合成（CTS）工具确定如何定位缓冲区的层次结构，以便将集成电路（IC）中的时钟信号扇出时钟设备（“sink”）。该工具首先聚集接收器，并在每个集群附近放置最低级别的扇出缓冲区。然后，该工具通过对最后放置的缓冲器级别进行聚类，然后在每个较低级缓冲区集群的质心附近放置下一个较高级别的缓冲区，直到工具将缓冲区放置在中间级别该级别和下一个较高缓冲器级别之间的路径距离超过预定限制。然后，CTS工具将中间缓冲区的质心放置一个顶级缓冲区，将布局划分为分区，每个分区包含相似数量的中间缓冲区，然后在每个分区中放置第二高级缓冲区。 CTS通过将每个分区划分为逐渐更小的分区并将逐级更低级缓冲区放置在每个较小的分区中，迭代地将每个下一个较低的缓冲区级别放置，直到它将缓冲区置于具有足够数量的缓冲区的级别来驱动中级缓冲区。

86. 发明申请

WO2004102339A2 REMOVAL OF ACUTE ANGLES IN A DESIGN LAYOUT 审中-公开
标题翻译：在设计布局中移除急性角膜
公开(公告)号：WO2004102339A2
公开(公告)日：2004-11-25
申请号：PCT/US2004/014380
申请日：2004-05-06
申请人： CADENCE DESIGN SYSTEMS, INC
发明人： JACQUES, Etienne , KRONMILLER, Tom
IPC分类号： G06F
CPC分类号： G06F1/00 , G06F15/00
摘要： Some embodiments of the invention provide novel methods for removing acute angles from routes in a design layout. The method selects a route with several segments. It then identifies an acute angle between first and second contiguous segments of the route. The method next inserts a third segment between the first and second segments, where the third segment has an associated shape that fills the acute angle between the first and second segments.
摘要翻译：本发明的一些实施例提供了用于在设计布局中从路线去除锐角的新颖方法。该方法选择具有多个段的路由。然后，它识别路线的第一和第二连续段之间的锐角。该方法接下来在第一和第二段之间插入第三段，其中第三段具有填充第一和第二段之间的锐角的相关联的形状。

87. 发明申请

WO2004008246A3 METHOD AND SYSTEM FOR CONTEXT-SPECIFIC MASK WRITING 审中-公开
标题翻译：用于上下文特征掩码的方法和系统
公开(公告)号：WO2004008246A3
公开(公告)日：2004-07-15
申请号：PCT/US0321996
申请日：2003-07-14
申请人： CADENCE DESIGN SYSTEMS INC
发明人： PACK ROBERT C , SHEFFER LOUIS K
IPC分类号： G03F20060101 , G03F1/00 , G03F1/36 , G03F1/78 , G03F7/20 , G03F9/00 , G06F17/50 , H01L21/027
CPC分类号： G03F1/68 , G03F1/36 , G03F1/78
摘要： A method for generating lithography masks 118 includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask 106.
摘要翻译：用于产生光刻掩模118的方法包括生成集成电路设计数据并使用来自集成电路设计数据的上下文信息来写入掩模106。

88. 发明申请

WO2004051403A2 METHOD, APPARATUS, AND SYSTEM FOR ROUTING 审中-公开
标题翻译：方法，装置和路由系统
公开(公告)号：WO2004051403A2
公开(公告)日：2004-06-17
申请号：PCT/US2003/036873
申请日：2003-11-18
申请人： CADENCE DESIGN SYSTEMS, INC. , FRANKLE, Jonathan , CALDWELL, Andrew , JACQUES, Etienne , TEIG, Steven
发明人： FRANKLE, Jonathan , CALDWELL, Andrew , JACQUES, Etienne , TEIG, Steven
IPC分类号： G06F
CPC分类号： G06F1/00 , G06F17/50
摘要： Some embodiments of the invention provide a method of identifying global routes for nets in a region of a layout with multiple layers. In the region, each net has a set of routable elements. The method partitions each layer of the region into several sub-regions. For each net, the method then identifies a route that connects the sub-regions that contain the net’s set of routable elements, where some routes have at least one non-Manhattan edge and traverse sub-regions on multiple layers. Some embodiments search for a three-dimensional global path between first and second sets of routable elements in a region of a layout that has multiple layers. These embodiments partition the region into several sub-regions. They then perform a path search to identify a path between a first set of sub-regions that contains the first-set elements and a second set of sub-regions that contain a second-set element. During the path search, these embodiments explore expansions along Manhattan and non-Manhattan routing directions between the sub-regions on a plurality of layers. Some embodiments define a routing graph that has several of nodes on several layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges between the nodes on each layer. On one layer, there is at least one set of edges that are neither orthogonal nor parallel to a set of edges on another layer. These embodiments then use the routing graph to identify routes.
摘要翻译：本发明的一些实施例提供了一种识别具有多个层的布局的区域中的网络的全局路由的方法。在该区域，每个网络具有一组可路由元素。该方法将该区域的每个层分成几个子区域。对于每个网络，该方法然后识别连接包含网络可路由元件集合的子区域的路由，其中一些路由具有至少一个非曼哈顿边缘并遍历多个层上的子区域。一些实施例在具有多个层的布局的区域中搜索第一和第二组可路由元件之间的三维全局路径。这些实施例将该区域划分成几个子区域。然后，他们执行路径搜索以识别包含第一集合元素的第一组子区域和包含第二集合元素的第二组子区域之间的路径。在路径搜索期间，这些实施例探索沿着曼哈顿的扩展和在多个层之间的子区域之间的非曼哈顿路由方向。一些实施例定义了在几个层上具有几个节点的路由图，其中每个节点表示层上的子区域。在图中，每层上的节点之间有一组边。在一层上，至少有一组边缘既不正交也不平行于另一层上的一组边缘。然后，这些实施例使用路由图来识别路由。

89. 发明申请

WO2003105187A2 OPTIMIZATION METHODS FOR ON-CHIP INTERCONNECT GEOMETRIES SUITABLE FOR ULTRA DEEP SUB-MICRON PROCESSES 审中-公开
标题翻译：适用于超深度次微米工艺的片上互连几何的优化方法
公开(公告)号：WO2003105187A2
公开(公告)日：2003-12-18
申请号：PCT/US2003/016164
申请日：2003-05-21
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： JUNG, Won-Young
IPC分类号： H01L
CPC分类号： G06F17/5036 , H01L21/76838 , H01L23/5222 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each of a number of optimized structures into one optimized interconnect process file, such as a process technology file for extractors. This optimized process technology file can use not only extracted interconnect process parameters but also the input of LPE (Layout Parasitic Extraction) tools in physical verification stage.
摘要翻译：本发明提出了用于互连几何形状的优化方法，其易于扩展到UDSM区域，用于比现有技术更实际和准确地确定片上互连工艺参数。一种用于将多个优化结构中的每一个重新组装成一个优化的互连处理文件（例如提取器的处理技术文件）的重建流程的方法。这种优化的过程技术文件不仅可以使用提取的互连过程参数，还可以在物理验证阶段使用LPE（布局寄生提取）工具的输入。

90. 发明申请

WO2003100704A3 ASSERTION-BASED TRANSACTION RECORDING 审中-公开
公开(公告)号：WO2003100704A3
公开(公告)日：2003-12-04
申请号：PCT/US2003/016996
申请日：2003-05-28
申请人： CADENCE DESIGN SYSTEMS, INC.
发明人： MARSCHNER, Franz, Erich , LAWRENCE, James, M. , WARD, Stephen, T.
IPC分类号： G06F17/50
摘要： An assertion based transaction recording method is used to represent a signal-level transaction having a prefix as an abstract transaction (101). The method models the signal-level transaction as an assertion requiring that the transaction suffix must occur following any occurrence of the transaction prefix. A finite-state-machine (FSM) implementation of the assertion records a tentative abstract transaction upon recognizing the first condition of the prefix (102). If the FSM recognizes that the prefix cannot complete, it cancels, or deletes, the tentative abstract transaction record. The implementation can track multiple tentative abstract transaction records that may co-exist prior to completion of the transaction prefix (104). Upon recognizing that the transaction prefix corresponding to the start point of the tentative abstract transaction has completed (104), the tentative abstract transaction record is committed (106). The FSM implementation of the assertion can then cancel all other outstanding tentative abstract transaction records.

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