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81. 发明授权

US06446503B1 Flow velocity measuring apparatus and methods using sensors for measuring larger and smaller flow quantities 失效
标题翻译：使用传感器测量更大和更小流量的流速测量装置和方法
公开(公告)号：US06446503B1
公开(公告)日：2002-09-10
申请号：US09577882
申请日：2000-05-25
申请人： Kazumitsu Nukui , Hideo Kato , Ken Tashiro , Mitunori Komaki , Masahiko Matushita , Kazuhiro Yamada
发明人： Kazumitsu Nukui , Hideo Kato , Ken Tashiro , Mitunori Komaki , Masahiko Matushita , Kazuhiro Yamada
IPC分类号： G01F700
CPC分类号： G01F7/00
摘要： A flowmeter capable of measuring an accurate quantity of flow over a wide range of the quantity of flow. A measurement zone (15) for smaller quantity of flow and a measurement zone (16) for larger quantity of flow are determined inside a flow path (13) of a pipe (10). Regulating strainers (14) for regulating the flow of a gas (20) are disposed inside the measurement zone (15) for smaller quantity of flow by dividing the flow path (13) into a plurality of narrower flow paths (14A). A mean flow velocity of the gas (20) flowing through each of a plurality of narrower flow paths (14A) becomes substantially equal. A part of the gas (20) reaches nozzles (22a, 22b) erected across flow velocity sensors (15a, 15b) for smaller quantity of flow and is accelerated by the operation of these nozzles. The flow velocity sensors (15a, 15b) inside the measurement zone (15) for smaller quantity of flow output signals corresponding to the flow velocity of the gas (20) passed through the narrower flow path (14a) and accelerated by the nozzles (22a, 22b) in the range of the smaller quantity of flow. Flow velocity sensors (16a, 16b) for larger quantity of flow in the measurement zone (16) for lager quantity of flow output signals corresponding to the flow velocity of the gas (20) in the range of the larger quantity of flow.
摘要翻译：一种流量计，能够在宽的流量范围内测量准确的流量。在管道（10）的流路（13）内确定用于较小流量的测量区域（15）和用于较大流量的测量区域（16）。用于调节气体（20）流动的调节过滤器（14）通过将流动路径（13）分成多个更窄的流动路径（14A）而设置在测量区域15的内部，用于较小的流量。流过多个较窄流路（14A）中的每一个的气体（20）的平均流速基本相等。气体（20）的一部分到达用于较少流量的跨越流速传感器（15a，15b）竖立的喷嘴（22a，22b），并且通过这些喷嘴的操作而加速。用于对应于通过较窄流路（14a）并被喷嘴（22a）加速的气体（20）的流速的较小量的流量输出信号的测量区域（15）内部的流速传感器（15a，15b），22b）在较小流量的范围内。用于在大量流量范围内对应于气体（20）的流速的较大量的流量输出信号的用于测量区域（16）中较大流量的流速传感器（16a，16b）。

82. 发明授权

US06243125B1 Optical printer head for an optical printer 失效
标题翻译：用于光学打印机的光学打印机头
公开(公告)号：US06243125B1
公开(公告)日：2001-06-05
申请号：US09392720
申请日：1999-09-09
申请人： Tomohiko Yuge , Toshiaki Nakahara , Hideo Kato , Yuuichi Kimura
发明人： Tomohiko Yuge , Toshiaki Nakahara , Hideo Kato , Yuuichi Kimura
IPC分类号： B41J1514
CPC分类号： B41J2/525 , B41J2/4476 , G02B27/0018
摘要： An optical printer head capable of minimizing production of a ghost by incidence of light reflected on a filter holding hole. Light emitted from a light source is reflected out of a maximum allowable incident angle to minimize generation of a ghost due to incidence of reflected light on a selfoc lens array while reducing a size of a filter holding hole for holding each of filters therein. Also, a peripheral surface of the filter holding hole may be rendered rough, to thereby provide a scattering surface, resulting in preventing repeated reflection of light emitted from the light source on the peripheral surface of the filter holding hole.
摘要翻译：一种光学打印头，其能够通过在过滤器保持孔上反射的光的入射来最小化重影的产生。从光源发射的光被从最大允许入射角反射，以最小化由于自发透镜阵列上的反射光的入射引起的重影的产生，同时减小用于保持每个滤光器的滤光器保持孔的尺寸。此外，过滤器保持孔的周边表面可能变得粗糙，从而提供散射表面，从而防止从光源发射的光在过滤器保持孔的外周表面上反复反射。

83. 发明授权

US06222779B1 Semiconductor storage device with automatic write/erase function 有权
标题翻译：具有自动写入/擦除功能的半导体存储设备
公开(公告)号：US06222779B1
公开(公告)日：2001-04-24
申请号：US09460644
申请日：1999-12-15
申请人： Hidetoshi Saito , Hideo Kato , Naoto Tomita , Tokumasa Hara
发明人： Hidetoshi Saito , Hideo Kato , Naoto Tomita , Tokumasa Hara
IPC分类号： G11C700
CPC分类号： G11C16/16 , G11C16/12
摘要： A semiconductor storage device, which has an automatic write/erase function, and uses a potential obtained by boosting a power supply voltage upon write/erase, has a write division control circuit which shifts the selection timings of bit lines upon write, so as to decrease the number of bits to be written simultaneously, thereby reducing the consumption current and compensating for insufficient current supply performance of a power supply circuit in case the power supply voltage is low, and refers to the contents of erase flags upon pre-programming in erase, and erase only blocks that require erases, while, when the power supply voltage is high as the power supply voltage has a wide range or the write time is short as in an acceleration test, the number of bits to be selected at the same time is increased to prevent an increase in write/erase time.
摘要翻译：具有自动写入/擦除功能并且使用通过在写入/擦除时提高电源电压而获得的电位的半导体存储装置具有写入分配控制电路，其在写入时移位位线的选择定时，以便减少要同时写入的位数，从而降低消耗电流并补偿在电源电压低的情况下电源电路的电流供应不足，并且在擦除预编程时参考擦除标志的内容，并且仅擦除需要擦除的块，而当电源电压为高电平时，电源电压具有较大的范围或写入时间短于加速度测试时，同时选择的位数增加以防止写入/擦除时间的增加。

84. 发明授权

US06187468B1 Electrodes for fuel cells 有权
标题翻译：燃料电池用电极
公开(公告)号：US06187468B1
公开(公告)日：2001-02-13
申请号：US09442617
申请日：1999-11-18
申请人： Hiroshi Shinkai , Ichirou Tanaka , Minako Onodera , Kazuhiko Iwasaki , Tsugio Ohba , Hideo Kato , Ichirou Baba
发明人： Hiroshi Shinkai , Ichirou Tanaka , Minako Onodera , Kazuhiko Iwasaki , Tsugio Ohba , Hideo Kato , Ichirou Baba
IPC分类号： H01M486
CPC分类号： H01M4/8828 , H01M4/8605 , H01M4/8803 , H01M4/92 , H01M4/926 , H01M8/1004 , Y10T29/49115
摘要： This invention provides an electrode for a fuel cell comprising a catalyst layer obtained by a first step of homogeneously mixing carbon supporting platinum which is an electrode catalyst, an alcohol solution of an ion conductive component which is a solid polymer electrolytic membrane component, and an organic solvent, by means of a stirrer having a grinding effect to produce electrode paste in which the carbon is highly dispersed; a second step of stirring said electrode paste by means of a three-dimensional vibrating stirrer in order to obtain highly structured carbon on which platinum is supported; and a third step of coating a gas diffusion electrode material and/or a solid polymer electrolytic membrane with the electrode paste in which the carbon is highly structured, followed by removal of the organic solvent.
摘要翻译：本发明提供一种燃料电池用电极，其具有将作为电极催化剂的碳负载铂，作为固体高分子电解质膜成分的离子传导性成分的醇溶液与有机物的均匀混合的第一工序，溶剂，通过具有研磨效果的搅拌器产生其中碳高度分散的电极浆料; 通过三维振动搅拌器搅拌所述电极浆料以获得负载铂的高度结构化的碳的第二步骤; 以及第三步骤，其中具有高度结构的碳的电极浆料涂覆气体扩散电极材料和/或固体聚合物电解质膜，然后除去有机溶剂。

85. 发明授权

US6094701A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6094701A
公开(公告)日：2000-07-25
申请号：US99841
申请日：1998-06-19
申请人： Yoshio Mochizuki , Hideo Kato
发明人： Yoshio Mochizuki , Hideo Kato
IPC分类号： G11C17/18 , G06F12/06 , G11C7/10 , G11C8/04 , G06F12/02
CPC分类号： G11C7/1018
摘要： A semiconductor memory device is provided with a determination circuit and an address adder. The determination circuit determines whether a read start address selects upper-address banks B5-B8 or lower-address banks B1-B4. When the determination circuit determines that the lower-address banks are selected, the address adder increments a column address by 1. From the upper-address banks, data are read from the columns corresponding to the read start address. From the lower-address banks, data are read from the columns that are next to the columns corresponding to the read start address. Even when the upper-address banks are designated by the read start address, the data output from the lower-address banks corresponds to the next columns. Since there is no busy time during data output, successive access is enabled and the access cycle time can be as short as possible.
摘要翻译：半导体存储器件具有确定电路和地址加法器。确定电路确定读取开始地址是否选择上位地址库B5-B8或低地址段B1-B4。当确定电路确定选择了较低地址组时，地址加法器将列地址递增1.从高地址组中，从与读取起始地址对应的列中读取数据。从较低地址库中，从与读取起始地址对应的列的旁边的列中读取数据。即使通过读取起始地址指定高地址组，从低地址组输出的数据对应于下一列。由于在数据输出期间没有繁忙时间，所以连续访问被使能，并且访问周期时间可以尽可能短。

86. 发明授权

US5924123A Semiconductor storage apparatus with copy guard function 失效
标题翻译：具有防拷功能的半导体存储设备
公开(公告)号：US5924123A
公开(公告)日：1999-07-13
申请号：US844947
申请日：1997-04-23
申请人： Yoshio Mochizuki , Hideo Kato
发明人： Yoshio Mochizuki , Hideo Kato
IPC分类号： G11C17/00 , G06F12/14 , G06F21/00 , G06F12/00
CPC分类号： G06F12/1433 , G06F12/1408 , G06F21/79
摘要： For copy guard, an ROM comprises an address data determining circuit, an address sequence monitoring circuit, an error address data generating circuit, and an output selection circuit. The address sequence monitoring circuit monitors the addresses stored in the address data determining circuit and input addresses to determine whether or not the input addresses are in a predetermined sequence of the addresses in the address data determining circuit. The output selection circuit outputs data read from said memory cell array when the address sequence monitoring circuit determines that the address sequence of the input addresses coincides with the predetermined sequence of the addresses stored in the address data determining circuit and outputs error data generated by the error data generating circuit when a determination is made that the sequence of the input addresses does not coincide with the predetermined sequence.
摘要翻译：对于复制保护，ROM包括地址数据确定电路，地址序列监视电路，错误地址数据产生电路和输出选择电路。地址序列监视电路监视存储在地址数据确定电路中的地址和输入地址，以确定输入地址是否在地址数据确定电路中的地址的预定顺序中。当地址序列监视电路确定输入地址的地址序列与存储在地址数据确定电路中的地址的预定序列一致时，输出选择电路输出从所述存储单元阵列读取的数据，并输出由该错误产生的错误数据当确定输入地址的序列与预定序列不一致时，数据产生电路。

87. 发明授权

US5773177A X-ray mask structure, and X-ray exposure process 失效
标题翻译： X射线掩模结构和X射线曝光处理
公开(公告)号：US5773177A
公开(公告)日：1998-06-30
申请号：US565215
申请日：1995-11-30
申请人： Tsutomu Ikeda , Masao Sugata , Hideo Kato
发明人： Tsutomu Ikeda , Masao Sugata , Hideo Kato
IPC分类号： G03F1/00 , G03F1/22 , G03F9/00
CPC分类号： G03F1/22
摘要： The present invention provides an X-ray mask structure having an X-ray transmissive membrane, an X-ray absorber held on an X-ray transmissive membrane, and a holding frame that holds the X-ray transmissive membrane, and the X-ray transmissive membrane has a layer of aluminum nitride, and the X-ray absorber has a heavy metal nitride.
摘要翻译：本发明提供一种X射线掩模结构，其具有X射线透过膜，X射线吸收体保持在X射线透过膜上，保持框架保持X射线透过膜，X射线透光膜具有氮化铝层，X射线吸收体具有重金属氮化物。

88. 发明授权

US5732022A Non-volatile semiconductor memory device 失效
公开(公告)号：US5732022A
公开(公告)日：1998-03-24
申请号：US812765
申请日：1997-03-06
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C16/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

89. 发明授权

US5576994A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5576994A
公开(公告)日：1996-11-19
申请号：US428060
申请日：1995-04-25
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C7/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问，与常规装置相比。

90. 发明授权

US5548559A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5548559A
公开(公告)日：1996-08-20
申请号：US448852
申请日：1995-05-24
申请人： Yoshio Mochizuki , Hideo Kato , Nobutake Sugiura
发明人： Yoshio Mochizuki , Hideo Kato , Nobutake Sugiura
IPC分类号： G06F12/06 , G11C8/12 , G11C16/20 , G11C17/00 , G11C8/00
CPC分类号： G11C16/20 , G11C8/12
摘要： A semiconductor integrated circuit includes a chip address data designation circuit, which has nonvolatile circuit characteristics or nonvolatilely programmed wiring corresponding to a chip address assigned to each of semiconductor chips connected to common buses, to output first chip address data corresponding to the chip address upon receiving an operation power supply voltage. The semiconductor integrated circuit further includes a chip address data latch circuit for latching second chip address data supplied from outside to the semiconductor chip, and a chip selection control circuit for comparing the first chip address data and the second chip address data, and generating a chip selection signal for activating the semiconductor chip when the first chip address data and the second chip address data coincide with each other. The chip address assigned to each semiconductor chip can be stored nonvolatilely, and one of the chips can be selected in response to the chip address supplied from outside the chip.
摘要翻译：半导体集成电路包括芯片地址数据指定电路，其具有对应于分配给连接到公共总线的每个半导体芯片的芯片地址的非易失性电路特性或非易失性编程布线，以在接收时输出与芯片地址对应的第一芯片地址数据操作电源电压。半导体集成电路还包括用于锁存从外部向半导体芯片提供的第二芯片地址数据的芯片地址数据锁存电路，以及用于比较第一芯片地址数据和第二芯片地址数据的芯片选择控制电路，以及产生芯片当第一芯片地址数据和第二芯片地址数据彼此一致时激活半导体芯片的选择信号。分配给每个半导体芯片的芯片地址可以被非易失性地存储，并且可以响应于从芯片外部提供的芯片地址来选择一个芯片。

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