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81. 发明授权

US08587062B2 Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts 有权
标题翻译：具有相邻体接触的绝缘体上硅（SOI）场效应晶体管（FET）
公开(公告)号：US08587062B2
公开(公告)日：2013-11-19
申请号：US11690975
申请日：2007-03-26
申请人： Jack A. Mandelman , Haining S. Yang
发明人： Jack A. Mandelman , Haining S. Yang
IPC分类号： H01L27/12
CPC分类号： H01L29/78615
摘要： A field effect transistor (FET) with an adjacent body contact, a SOI IC with circuits including the FETs and a method of fabricating the ICs. Device islands are formed in the silicon surface layer of a SOI wafer. Gates are defined on the wafer. Body contacts are formed in a perimeter conductive region adjacent to the gates. The body contacts may be either a silicide strap along the gate sidewall at one side of the FET or a separate contact separated from the gate by a dielectric stripe at one side of the FET. Separate contacts may be connected to a bias supply.
摘要翻译：具有相邻体接触的场效应晶体管（FET），具有包括FET的电路的SOI IC和制造IC的方法。器件岛形成在SOI晶片的硅表面层中。盖子被定义在晶圆上。主体触点形成在与栅极相邻的周边导电区域中。主体触点可以是沿FET的一侧的栅极侧壁的硅化物带或通过FET一侧的介电条与栅极分开的单独触点。单独的触点可能连接到偏置电源。

82. 发明授权

US08361704B2 Method for reducing tip-to-tip spacing between lines 有权
标题翻译：减少线间距尖端间距的方法
公开(公告)号：US08361704B2
公开(公告)日：2013-01-29
申请号：US12352051
申请日：2009-01-12
申请人： Matthew E. Colburn , Wai-kin Li , Haining S. Yang
发明人： Matthew E. Colburn , Wai-kin Li , Haining S. Yang
IPC分类号： G03F7/20
CPC分类号： G03F7/40 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： This invention provides a method for reducing tip-to-tip spacing between lines using a combination of photolithographic and copolymer self-assembling lithographic techniques. A mask layer is first formed over a substrate with a line structure. A trench opening of a width d is created in the mask layer. A layer of a self-assembling block copolymer is then applied over the mask layer. The block copolymer layer is annealed to form a single unit polymer block of a width or a diameter w which is smaller than d inside the trench opening. The single unit polymer block is selectively removed to form a single opening of a width or a diameter w inside the trench opening. An etch transfer process is performed using the single opening as a mask to form an opening in the line structure in the substrate.
摘要翻译：本发明提供了使用光刻和共聚物自组装光刻技术的组合来减少线之间的尖端到尖端间隔的方法。首先在具有线结构的衬底上形成掩模层。在掩模层中形成宽度为d的沟槽开口。然后将一层自组装嵌段共聚物施加在掩模层上。对嵌段共聚物层进行退火以在沟槽开口内形成宽度或直径w小于d的单一单元聚合物嵌段。选择性地去除单个单元聚合物嵌段以在沟槽开口内形成宽度或直径w的单个开口。使用单个开口作为掩模进行蚀刻转印处理，以在基板中的线结构中形成开口。

83. 发明申请

US20120214301A1 STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING 有权
标题翻译：用电流保险丝形式提高电流消耗的结构和方法
公开(公告)号：US20120214301A1
公开(公告)日：2012-08-23
申请号：US13453165
申请日：2012-04-23
申请人： Deok-Kee Kim , Ahmet S. Ozcan , Haining S. Yang
发明人： Deok-Kee Kim , Ahmet S. Ozcan , Haining S. Yang
IPC分类号： H01L21/28
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
摘要翻译：电熔丝结构和方法具有阳极; 熔丝连接（熔丝连接的第一端连接到阳极）; 阴极（与第一端相对的熔断体的第二端连接到阴极）; 和熔丝链上的硅化物层。硅化物层具有邻近阳极的第一硅化物区域和与阴极相邻的第二硅化物区域。第二硅化物区域包括不包含在第一硅化物区域内的杂质。此外，第一硅化物区域比第二硅化物区域薄。

84. 发明授权

US08093644B2 Multiwalled carbon nanotube memory device 失效
标题翻译：多壁碳纳米管记忆装置
公开(公告)号：US08093644B2
公开(公告)日：2012-01-10
申请号：US12350432
申请日：2009-01-08
申请人： Haining S. Yang
发明人： Haining S. Yang
IPC分类号： H01L21/00
CPC分类号： H01L51/0558 , B82Y10/00 , G11C13/025 , G11C16/0416 , G11C2213/17 , H01L21/28273 , H01L29/0665 , H01L29/0673 , H01L29/1606 , H01L51/0048 , Y10S977/742 , Y10S977/939
摘要： A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.
摘要翻译：一种基于碳纳米管的存储器件包括一组具有不同直径的三个同心碳纳米管。选择三个同心碳纳米管的直径使得内部碳纳米管是半导体的，并且在相邻的碳纳米管之间发生壳内电子传递。对内部碳纳米管进行源极和漏极接触，并对外部碳纳米管进行栅极接触。基于碳纳米管的存储器件通过在壳碳纳米管中通过壳电子传输存储电子或空穴进行编程。检测由于中间壳中的电荷导致的内部碳纳米管的电导率的变化，以确定中间碳纳米管的电荷状态。因此，基于碳纳米管的存储装置以电荷的形式将信息存储在中间碳纳米管中。

85. 发明授权

US07973409B2 Hybrid interconnect structure for performance improvement and reliability enhancement 有权
标题翻译：混合互连结构，用于性能改进和可靠性提升
公开(公告)号：US07973409B2
公开(公告)日：2011-07-05
申请号：US11625576
申请日：2007-01-22
申请人： Chih-Chao Yang , Thomas M. Shaw , Keith Kwong Hon Wong , Haining S. Yang
发明人： Chih-Chao Yang , Thomas M. Shaw , Keith Kwong Hon Wong , Haining S. Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/76841 , H01L21/7682 , H01L21/76831 , H01L23/481 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
摘要翻译：本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地，气隙。与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

86. 发明授权

US07863653B2 Method of enhancing hole mobility 有权
标题翻译：增强空穴迁移率的方法
公开(公告)号：US07863653B2
公开(公告)日：2011-01-04
申请号：US11561496
申请日：2006-11-20
申请人： Henry K. Utomo , Judson R. Holt , Haining S. Yang
发明人： Henry K. Utomo , Judson R. Holt , Haining S. Yang
IPC分类号： H01L27/10
CPC分类号： H01L27/1203 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/78687
摘要： A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same crystalline orientation. The device further includes a graded germanium layer on the first silicon layer, wherein the graded germanium layer contacts a spacer and the first silicon layer and does not contact the oxide layer. A lower portion of the graded germanium layer comprises a higher concentration of germanium than an upper portion of the graded germanium layer, wherein a top surface of the graded germanium layer lacks germanium.
摘要翻译：提供一种半导体器件，其包括位于氧化物层之上的第一硅层和第二硅层上的氧化物层，其中氧化物层位于第一硅层和第二硅层之间。第一硅层和第二硅层包含相同的晶体取向。所述器件还包括在所述第一硅层上的分级锗层，其中所述分级锗层接触间隔物和所述第一硅层并且不接触所述氧化物层。分级锗层的下部包含比分级锗层的上部更高浓度的锗，其中分级锗层的顶表面缺少锗。

87. 发明授权

US07851885B2 Methods and systems involving electrically programmable fuses 有权
标题翻译：涉及电气可编程保险丝的方法和系统
公开(公告)号：US07851885B2
公开(公告)日：2010-12-14
申请号：US11847379
申请日：2007-08-30
申请人： Deok-kee Kim , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
发明人： Deok-kee Kim , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.
摘要翻译：一种电可编程保险丝，包括阴极构件，阳极构件和连接构件，其中所述阴极构件，所述阳极构件和所述连接构件各自包括可操作地定位所述可编程熔丝中的感应电迁移的多种材料中的一种。

88. 发明申请

US20100237460A9 METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES 有权
标题翻译：涉及电气可编程熔丝的方法和系统
公开(公告)号：US20100237460A9
公开(公告)日：2010-09-23
申请号：US11847379
申请日：2007-08-30
申请人： Deok-kee Kim , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
发明人： Deok-kee Kim , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.
摘要翻译：一种电可编程保险丝，包括阴极构件，阳极构件和连接构件，其中所述阴极构件，所述阳极构件和所述连接构件各自包括可操作地定位所述可编程熔丝中的感应电迁移的多种材料中的一种。

89. 发明授权

US07790558B2 Method and apparatus for increase strain effect in a transistor channel 有权
标题翻译：在晶体管通道中增加应变效应的方法和装置
公开(公告)号：US07790558B2
公开(公告)日：2010-09-07
申请号：US11465663
申请日：2006-08-18
申请人： Haining S. Yang , Huilong Zhu
发明人： Haining S. Yang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/66545 , H01L29/7842
摘要： Method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate. The method utilizes depositing a nitride film along a surface of the substrate and the gate stack. The nitride film is thicker over a surface of the substrate and thinner over a portion of the gate stack.
摘要翻译：在具有设置在基板上的栅极堆叠的半导体器件中增强应力的方法。该方法利用沿着衬底的表面和栅叠层沉积氮化物膜。氮化物膜在衬底的表面上更厚，并且在栅极堆叠的一部分上更薄。

90. 发明授权

US07785937B2 Electrical fuse having sublithographic cavities thereupon 失效
公开(公告)号：US07785937B2
公开(公告)日：2010-08-31
申请号：US12561689
申请日：2009-09-17
申请人： Deok-kee Kim , Wai-Kin Li , Haining S. Yang
发明人： Deok-kee Kim , Wai-Kin Li , Haining S. Yang
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , Y10T29/49107 , H01L2924/00
摘要： An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.

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