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81. 发明授权

US4638868A Earth engaging implements 失效
标题翻译：地球接合工具
公开(公告)号：US4638868A
公开(公告)日：1987-01-27
申请号：US716624
申请日：1985-03-27
申请人： William M. Johnson , Ilmar Mere
发明人： William M. Johnson , Ilmar Mere
IPC分类号： A01B15/02 , A01B35/22 , A01B23/02
CPC分类号： A01B15/025 , A01B35/225
摘要： An earth engaging implement and tine construction comprising a tine having bolted thereto an adaptor having an upper surface externally tapered in cross section, an elongated slot extending through the adaptor to receive a bolt head, and the lower surface of the adaptor comprising a rediused portion and a flat portion. An earth engaging implement includes an earth engaging portion and an attachment portion, the attachment portion comprising a tapered socket of complementary cross sectional shape to the upper surface of the adaptor, and the earth engaging implement being secured to the adaptor by a wedging frictional grip on to the upper surface. The adaptor has an angle of inclination of the upper surface thereof when mounted on the tine which corresponds to the angle of attachment portion of the earth engaging implement when it is oriented for ground engagement.
摘要翻译：一种地面接合工具和齿构造，其包括具有螺栓连接到其上的具有横截面为外锥形的上表面的适配器的齿，延伸穿过适配器以容纳螺栓头的细长槽，并且适配器的下表面包括重新连接的部分和平坦部分。地面接合工具包括地面接合部分和附接部分，所述附接部分包括与适配器的上表面互补的横截面形状的锥形插座，并且接地工具通过楔形摩擦把手固定到适配器上到上表面。适配器当安装在与地面接合工具的附接部分的角度相对应的齿上时，其上表面具有倾斜角度，当其被定向成接地接合时。

82. 外观设计

USD277862S Agricultural sweep 失效
公开(公告)号：USD277862S
公开(公告)日：1985-03-05
申请号：US299218
申请日：1981-09-03
申请人： William M. Johnson , Allan Lindsay
设计人： William M. Johnson , Allan Lindsay

83. 发明授权

US4364199A Removable-tilt-out window construction 失效
标题翻译：可拆卸倾斜窗构造
公开(公告)号：US4364199A
公开(公告)日：1982-12-21
申请号：US167580
申请日：1980-07-11
申请人： William M. Johnson , Kelly L. Calhoon
发明人： William M. Johnson , Kelly L. Calhoon
IPC分类号： E05D15/22
CPC分类号： E05D15/22 , E05Y2900/148
摘要： The invention relates to a removable tilt-out window construction in which a window may be rotated 90.degree. from its normal vertical position and such rotation causes a slidable block connected to a spring counterbalance to be locked in place to prevent violent release of the spring upon removal of the window. The invention describes a weather strip (30) having a slidable block (68) with a rotatable locking cam (90). Slidable block (68) rides on tracks (64 and 66). Locking Cam (90) can be rotated so that it forces tracks (64 and 66) against the sides of slots (110 and 112) to frictionally engage the slidable block (68) into a fixed position. A window sash (22) is connected to the locking cam (90) to provide rotation thereof to lock slidable block (68). Window 22 may be removed from engagement with locking cam (90) if desired.
摘要翻译：本发明涉及一种可拆卸的倾斜窗结构，其中窗口可以从其正常垂直位置旋转90°，并且这种旋转使得连接到弹簧平衡面的可滑动块被锁定到位以防止弹簧暴露于拆除窗户。本发明描述了具有带有可旋转锁定凸轮（90）的可滑动块（68）的防风条（30）。可滑动块（68）骑在轨道（64和66）上。锁定凸轮（90）可以旋转，使得其将轨道（64和66）抵靠槽（110和112）的侧面摩擦地接合到可固定位置。窗扇（22）连接到锁定凸轮（90）以提供其旋转以锁定可滑动块（68）。如果需要，窗口22可以与锁定凸轮（90）脱离啮合。

84. 发明授权

US09552206B2 Integrated circuit with control node circuitry and processing circuitry 有权
标题翻译：具有控制节点电路和处理电路的集成电路
公开(公告)号：US09552206B2
公开(公告)日：2017-01-24
申请号：US13232774
申请日：2011-09-14
申请人： William M. Johnson , Murali S. Chinnakonda , Jeffrey L. Nye , Toshio Nagata , John W. Glotzbach , Hamid R. Sheikh , Ajay Jayaraj , Stephen Busch , Shalini Gupta , Robert J.P. Nychka , David H. Bartley , Ganesh Sundararajan
发明人： William M. Johnson , Murali S. Chinnakonda , Jeffrey L. Nye , Toshio Nagata , John W. Glotzbach , Hamid R. Sheikh , Ajay Jayaraj , Stephen Busch , Shalini Gupta , Robert J.P. Nychka , David H. Bartley , Ganesh Sundararajan
IPC分类号： G06F15/16 , G06F15/80 , G06F9/30 , G06F9/355 , G06F9/38 , G06F9/45
CPC分类号： G06F9/30076 , G06F8/40 , G06F9/30 , G06F9/30054 , G06F9/30101 , G06F9/3012 , G06F9/355 , G06F9/3552 , G06F9/3853 , G06F9/3887 , G06F9/3891 , G06F15/16 , G06F15/80 , G06F15/8053
摘要： Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.
摘要翻译：传统上，在多核系统中提供并行处理非常困难。然而，这里提供了一种系统，其中串行源代码被自动转换为并行源代码，并且“即时”重新配置处理集群，以根据存储器和计算资源的分配来容纳并行化代码。因此，处理集群及其相应的系统编程工具提供可以对从用户透明的串行程序执行并行处理的系统。通常，连接到主处理器的地址和数据引线的控制节点使用消息来控制处理集群中的数据的处理。集群包括并行处理器的节点，共享功能存储器，全局加载/存储以及所有通过消息总线连接到控制节点的硬件加速器。交叉开关数据互连将数据路由到与消息总线分离的集群电路。

85. 发明申请

US20150326304A1 WORLD-WIDE, WIDE-BAND, LOW-LATENCY, MOBILE INTERNET AND SYSTEM THEREFOR 审中-公开
标题翻译：世界，宽带，低端，移动互联网及其系统
公开(公告)号：US20150326304A1
公开(公告)日：2015-11-12
申请号：US14717260
申请日：2015-05-20
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： H04B7/195 , H04B7/185
CPC分类号： H04B7/195 , H04B7/18523 , H04B10/118
摘要： A communication system for providing world-wide, mobile Internet communication to a plurality of users and a method therefore.The system includes ground-based, multi-channel, radio frequency transmitting and receiving broadcasting grids that are capable of providing content to multiple users via cell towers and low-altitude, optical transmitting and receiving satellites that are in optical communication with the ground-based, multi-channel, RF transmitting and receiving broadcasting grids. The method includes transmitting optical and/or RF signals between at least one of the ground-based, multi-channel, RF transmitting and receiving broadcasting grids and at least one of the low-altitude, optical transmitting and receiving satellites.
摘要翻译：一种用于向多个用户提供世界范围的移动因特网通信的通信系统及其方法。该系统包括基于地面，多通道，射频发射和接收的广播网格，能够通过经由小区塔和与地面光通信的低空，光发射和接收卫星向多个用户提供内容，多通道，射频发射和接收广播电网。该方法包括在地面，多声道，RF发射和接收广播网格中的至少一个和低空，光发射和接收卫星中的至少一个之间传输光信号和/或RF信号。

86. 发明申请

US20130307859A1 Processor, System, and Method for Efficient, High-Throughput Processing of Two-Dimensional, Interrelated Data Sets 有权
公开(公告)号：US20130307859A1
公开(公告)日：2013-11-21
申请号：US13602958
申请日：2012-09-04
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： G06F13/00 , G06T1/60 , G06F15/00
CPC分类号： G06T1/20 , G06F9/30043 , G06F9/3814 , G06F9/3824 , G06F9/3887 , G06F9/3893 , G06F15/80 , G06T1/60
摘要： Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage. This approach enables programmable visual computing with throughput approaching that of hardwired solutions.

87. 发明申请

US20110297794A1 METHOD OF NAVIGATING A SPINNING, ARTIFICIAL SATELLITE AND CONTROLLING THE GLOBAL, TERRESTRIAL SURVEILLANCE COVERAGE THEREOF 失效
标题翻译：引导旋转，人造卫星和控制全球，地面监测范围的方法
公开(公告)号：US20110297794A1
公开(公告)日：2011-12-08
申请号：US13212433
申请日：2011-08-18
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： B64G1/28 , B64G1/66
CPC分类号： B64G1/281 , B64G1/1007 , B64G1/1085 , B64G1/242 , B64G1/32 , B64G1/361 , B64G1/363 , B64G1/365 , B64G1/44 , G01S3/7862 , G01S3/7867 , G05D1/0883
摘要： A method of controlling inertial attitude of an artificial satellite in order to perform a navigation function and to maximize terrestrial coverage of the Earth by the satellite. The method includes deploying the artificial satellite in an orbit about the poles of the Earth; applying gyroscopic precession to the artificial satellite spin axis to precess and maintain the satellite near the ecliptic pole; deploying the artificial satellite so that the spin axis is initially perpendicular to or substantially perpendicular to sun lines; and applying gyroscopic precession to the artificial satellite spin axis to precess the spin axis away from an initial deployed attitude at a selectively-variable precession rate and to maintain the spin axis perpendicular to or substantially perpendicular to a the sun lines.
摘要翻译：控制人造卫星的惯性姿态以便执行导航功能并使卫星的地球覆盖范围最大化的方法。该方法包括将人造卫星部署在围绕地球两极的轨道上; 对人造卫星旋转轴进行陀螺进动，以使卫星靠近黄道; 部署人造卫星使得旋转轴线最初垂直于或基本垂直于太阳线; 以及将陀螺进动应用于人造卫星旋转轴线，以使旋转轴线以选择性可变的进动速率远离初始展开姿态，并且保持旋转轴垂直于或基本垂直于太阳线。

88. 发明授权

US5867683A Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations 失效
标题翻译：包括通用重排序缓冲器和普通寄存器文件的高性能超标量微处理器的方法，用于整数和浮点运算
公开(公告)号：US5867683A
公开(公告)日：1999-02-02
申请号：US845978
申请日：1997-04-30
申请人： David B. Witt , William M. Johnson
发明人： David B. Witt , William M. Johnson
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F15/167
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3822 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.
摘要翻译：提供了一种超标量微处理器，其包括共享高性能主数据处理总线的整数功能单元和浮点功能单元。整数单元和浮点单元还共享共同的重排序缓冲器，寄存器文件，分支预测单元和所有驻留在同一主数据处理总线上的加载/存储单元。指令和数据高速缓存通过处理其间的通信的内部地址数据总线耦合到主存储器。指令解码器耦合到指令高速缓存，并且能够每个微处理器周期解码多个指令。指令以推测顺序从解码器发出，发出无序，完成无序。指令从重新排序缓冲区中重新排序到寄存器文件。微处理器的功能单元期望地容纳显示多个数据宽度的操作数。通过所公开的超标量微处理器的共享架构来实现微处理器管芯尺寸的高性能和高效率的使用。

89. 发明授权

US5828869A Microprocessor arranged for synchronously accessing an external memory with a scalable clocking mechanism 失效
标题翻译：微处理器被布置成用可扩展的时钟机制同步访问外部存储器
公开(公告)号：US5828869A
公开(公告)日：1998-10-27
申请号：US878676
申请日：1997-06-19
申请人： William M. Johnson , David B. Witt
发明人： William M. Johnson , David B. Witt
IPC分类号： G06F12/00 , G06F1/08 , G06F13/16 , G06F13/40 , G06F13/42 , G06F15/78 , H03K19/0175 , G06F1/06 , G06F13/00
CPC分类号： G06F13/1689 , G06F1/08 , G06F13/4072 , G06F13/4243
摘要： A microprocessor is provided which is capable of executing synchronous accesses to an external memory whether the external memory is operating at the same frequency as the operating frequency of the microprocessor or whether the external memory is operating at a frequency which is one-half the microprocessor operating frequency. The microprocessor includes a rate control input for receiving a rate control signal having a first level indicative of the microprocessor frequency being equal to the external memory frequency or a second level indicative of the microprocessor frequency being twice the external memory frequency. A memory access control is coupled to the rate control input and is responsive to the rate control signal, an internal microprocessor clock, and the external memory clock for causing the microprocessor to access the external memory in synchronism with the external memory clock when the external memory frequency is either equal to the microprocessor frequency or is one-half the microprocessor frequency.
摘要翻译：提供了一种微处理器，其能够执行与外部存储器的同步访问，无论外部存储器是否以与微处理器的工作频率相同的频率操作，或外部存储器是否以微处理器操作的一半的频率操作频率。微处理器包括用于接收速率控制信号的速率控制信号，该速率控制信号具有指示微处理器频率等于外部存储器频率的第一电平，或指示微处理器频率是外部存储器频率的两倍的第二电平。存储器访问控制被耦合到速率控制输入端，并且响应于速率控制信号，内部微处理器时钟和外部存储器时钟，用于当外部存储器与外部存储器时钟同步地使得微处理器与外部存储器时钟同步地访问外部存储器频率等于微处理器频率或微处理器频率的一半。

90. 发明授权

US5758114A High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor 失效
标题翻译：高速指令对齐单元，用于根据超标量微处理器中的预编码信息对齐可变字节长度指令
公开(公告)号：US5758114A
公开(公告)日：1998-05-26
申请号：US864580
申请日：1997-05-28
申请人： William M. Johnson , David B. Witt , Thang Tran
发明人： William M. Johnson , David B. Witt , Thang Tran
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3816 , G06F9/30152 , G06F9/382
摘要： An instruction alignment unit is provided which transfers a fixed number of instructions from an instruction cache to each of a plurality of decode units. The instructions are selected from a quantity of bytes according to a predecode tag generated by a predecode unit. The predecode tag includes start-byte bits that indicate which bytes within the quantity of bytes are the first byte of an instruction. The instruction alignment unit independently scans a plurality of groups of instruction bytes, selecting start bytes and a plurality of contiguous bytes for each of a plurality of issue positions. Initially, the instruction alignment unit selects a group of issue positions for each of the plurality of groups of instructions. The instruction alignment unit then shifts and merges the independently produced issue positions to produce a final set of issue positions for transfer to a plurality of decode units.
摘要翻译：提供了一种指令对准单元，其将固定数量的指令从指令高速缓存传送到多个解码单元中的每一个。根据由预解码单元生成的预解码标签，从指定的字节数中选择指令。预解码标签包括开始字节位，指示字节数量中的哪个字节是指令的第一个字节。指令对准单元独立地扫描多组指令字节，为多个发行位置中的每一个选择开始字节和多个连续字节。最初，指令对准单元为多组指令中的每一组选择一组发行位置。然后，指令对准单元移动并合并独立产生的发行位置，以产生用于传送到多个解码单元的最后一组发行位置。

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