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81. 发明授权

US07315932B2 Data processing system having instruction specifiers for SIMD register operands and method thereof 有权
标题翻译：具有用于SIMD寄存器操作数的指令说明符的数据处理系统及其方法
公开(公告)号：US07315932B2
公开(公告)日：2008-01-01
申请号：US10657331
申请日：2003-09-08
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F15/80 , G06F15/82
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30109 , G06F9/30112
摘要： Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.
摘要翻译：可以使用各种加载和存储指令来在寄存器文件和存储器中的寄存器之间传送多个向量元素。可以使用cnt参数来指示要传送到存储器或从存储器传送的元素的总数，并且可以使用rcnt参数来指示可以传送到寄存器文件中的单个寄存器的向量元素的最大数量。此外，指令可以使用各种不同的寻址模式。可以独立于寄存器元件大小指定存储器元件大小，使得源和目标大小在指令内可能不同。通过一些指令，可以启动向量流并有条件地排队或出队。可以提供截断或舍入字段，使得源数据元素在被传送时可以被截断或舍入。此外，源数据元素在传输时可以是符号或无符号扩展的。

82. 发明申请

US20070300044A1 METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR 有权
公开(公告)号：US20070300044A1
公开(公告)日：2007-12-27
申请号：US11426633
申请日：2006-06-27
申请人： William C. Moyer , Kevin B. Traylor
发明人： William C. Moyer , Kevin B. Traylor
IPC分类号： G06F15/00
CPC分类号： G06F9/3877 , G06F9/3001 , G06F9/3824
摘要： A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).

83. 发明授权

US07228401B2 Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor 有权
标题翻译：将处理器连接到协处理器，其中处理器选择性地广播或选择性地改变协处理器的执行模式
公开(公告)号：US07228401B2
公开(公告)日：2007-06-05
申请号：US10054577
申请日：2001-11-13
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F15/163
CPC分类号： G06F9/3877
摘要： The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to selectively broadcast an operand that is being written to a register within the processor to a coprocessor communication bus. Each broadcast specifier may therefore include a broadcast indicator corresponding to each general purpose register of the processor. An alternate embodiment may also use the concept of broadcast regions where each broadcast region may have a corresponding broadcast specifier where one broadcast specifier may correspond to multiple broadcast regions. Alternatively, in one embodiment, the processor may use broadcast regions independent of the broadcast specifiers where the coprocessor is able to alter its functionality in response to the current broadcast region. In one embodiment, the processor may provide a region specifier via the coprocessor communication bus to indicate the current broadcast region.
摘要翻译：本发明一般涉及将处理器与至少一个协处理器进行接口。一个实施例涉及具有一组广播说明符的处理器，其用于选择性地将正在写入处理器内的寄存器的操作数广播到协处理器通信总线。因此，每个广播说明符可以包括对应于处理器的每个通用寄存器的广播指示符。替代实施例也可以使用广播区域的概念，其中每个广播区域可以具有相应的广播说明符，其中一个广播说明符可以对应于多个广播区域。或者，在一个实施例中，处理器可以使用独立于广播指定符的广播区域，其中协处理器能够响应于当前广播区域而改变其功能。在一个实施例中，处理器可以经由协处理器通信总线提供区域说明符以指示当前广播区域。

84. 发明授权

US07185148B2 Read access and storage circuitry read allocation applicable to a cache 有权
标题翻译：读访问和存储电路读取分配适用于缓存
公开(公告)号：US07185148B2
公开(公告)日：2007-02-27
申请号：US11197830
申请日：2005-08-05
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F11/3648 , G06F12/0888 , G06F12/126
摘要： A read allocation indicator (e.g. read allocation signal 30) is provided to storage circuitry (e.g. cache 22) to selectively determine whether read allocation will be performed for the read access. Read allocation may include modification of the information content of the cache (22) and/or modification of the read replacement algorithm state implemented by the read allocation circuitry (70) in cache (22). For certain types of debug operations, it may be very useful to provide a read allocation indicator that ensures that no unwanted modification are made to the storage circuitry during a read access. Yet other types of debug operations may want the storage circuitry to be modified in the standard manner when a read access occurs.
摘要翻译：将读分配指示符（例如，读分配信号30）提供给存储电路（例如，高速缓存22），以选择性地确定是否将对读访问执行读分配。读分配可以包括对高速缓存（22）中的读分配电路（70）实现的对高速缓存（22）的信息内容的修改和/或修改读取的替换算法状态。对于某些类型的调试操作，提供读取分配指示符可能是非常有用的，该读取分配指示符确保在读取访问期间不对存储电路进行不需要的修改。当读取访问发生时，其他类型的调试操作可能希望以标准方式修改存储电路。

85. 发明授权

US06832280B2 Data processing system having an adaptive priority controller 有权
标题翻译：数据处理系统具有自适应优先级控制器
公开(公告)号：US06832280B2
公开(公告)日：2004-12-14
申请号：US09927123
申请日：2001-08-10
申请人： Afzal M. Malik , William C. Moyer , William C. Bruce, Jr.
发明人： Afzal M. Malik , William C. Moyer , William C. Bruce, Jr.
IPC分类号： G06F1200
CPC分类号： G06F13/18 , G06F13/36
摘要： The present invention relates generally to data processors and more specifically, to data processors having an adaptive priority controller. One embodiment relates to a method for prioritizing requests in a data processor (12) having a bus interface unit (32). The method includes receiving a first request from a first bus requesting resource (e.g. 30) and a second request from a second bus requesting resource (e.g. 28), and using a threshold corresponding to the first or second bus requesting resource to prioritize the first and second requests. The first and second bus requesting resources may be a push buffer (28) for a cache, a write buffer (30), or an instruction prefetch buffer (24). According to one embodiment, the bus interface unit (32) includes a priority controller (34) that receives the first and second requests, assigns the priority, and stores the threshold in a threshold register (66). The priority controller (34) may also include one or more threshold registers (66), subthreshold registers (68), and control registers (70).
摘要翻译：本发明一般涉及数据处理器，更具体地说，涉及具有自适应优先级控制器的数据处理器。一个实施例涉及一种用于在具有总线接口单元（32）的数据处理器（12）中对请求进行优先级排序的方法。该方法包括从第一总线接收请求资源（例如30）的第一请求和来自第二总线请求资源（例如28）的第二请求，以及使用对应于第一或第二总线请求资源的阈值来优先处理第一和/ 第二个请求第一和第二总线请求资源可以是用于高速缓冲存储器的缓冲器（28），写入缓冲器（30）或指令预取缓冲器（24）。根据一个实施例，总线接口单元（32）包括优先级控制器（34），其接收第一和第二请求，分配优先级，并将阈值存储在阈值寄存器（66）中。优先级控制器（34）还可以包括一个或多个阈值寄存器（66），子阈值寄存器（68）和控制寄存器（70）。

86. 发明授权

US06775765B1 Data processing system having instruction folding and method thereof 有权
标题翻译：具有指令折叠的数据处理系统及其方法
公开(公告)号：US06775765B1
公开(公告)日：2004-08-10
申请号：US09498814
申请日：2000-02-07
申请人： Lea Hwang Lee , William C. Moyer
发明人： Lea Hwang Lee , William C. Moyer
IPC分类号： G06F938
CPC分类号： G06F9/325 , G06F9/30058 , G06F9/3017 , G06F9/324 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F9/3838 , G06F9/3842
摘要： Embodiments of the present invention relate generally to data processing systems having instruction folding and methods for controlling execution of a program loop. One embodiment includes detecting execution of a program loop and prefetching data in response to detecting execution of the program loop. Another embodiment includes detecting execution of a program loop and scanning the program loop for remote independent instructions or data dependencies during at least one iteration. Another embodiment includes detecting execution of a program loop and storing intra-loop data dependency information in a dependency bit vector, and using the dependency bit vector to select at least one local independent instruction available for folding. One embodiment includes an instruction folding unit comprising a first controller, a second controller, and a storage unit coupled to the second controller. Another embodiment includes a data processing system comprising a validation counter and a storage unit coupled to the validation counter where the storage unit includes a dependency bit vector corresponding to instructions of a program loop.
摘要翻译：本发明的实施例一般涉及具有指令折叠的数据处理系统和用于控制程序循环执行的方法。一个实施例包括响应于检测到程序循环的执行来检测程序循环的执行和预取数据。另一个实施例包括在至少一次迭代期间检测程序循环的执行和扫描用于远程独立指令或数据依赖性的程序循环。另一个实施例包括检测程序循环的执行并将循环中的数据依赖性信息存储在依赖性位向量中，并且使用相关性位向量来选择可用于折叠的至少一个本地独立指令。一个实施例包括指令折叠单元，包括第一控制器，第二控制器和耦合到第二控制器的存储单元。另一个实施例包括数据处理系统，其包括验证计数器和耦合到验证计数器的存储单元，其中存储单元包括与程序循环的指令相对应的依赖性位向量。

87. 发明授权

US06751724B1 Method and apparatus for instruction fetching 失效
标题翻译：指令取出方法和装置
公开(公告)号：US06751724B1
公开(公告)日：2004-06-15
申请号：US09552118
申请日：2000-04-19
申请人： William C. Moyer , Jeffrey W. Scott , James S. Thomas , John H. Arends , John J. Vaglica
发明人： William C. Moyer , Jeffrey W. Scott , James S. Thomas , John H. Arends , John J. Vaglica
IPC分类号： G06F930
CPC分类号： G06F9/3814 , G06F9/3802
摘要： Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor (202) to execute instructions and to fetch instructions from a memory (208) according to a fetch size. This data processor (202) comprises a first input (212) to receive instructions, control logic (402) to decode the instructions, and an instruction pipeline (400) coupled to the first input (212) and the control logic (400). The instruction pipeline (400) is responsive to a first signal (214) to set the fetch size to one of a first size and a second size. The data processor (202) therefore allows an instruction fetch policy to be altered based on the characteristics of an accessed device in order to achieve improved performance.
摘要翻译：本发明的实施例涉及在数据处理系统中的指令取出。一个方面涉及一种数据处理器（202），用于执行指令并根据取出大小从存储器（208）获取指令。该数据处理器（202）包括用于接收指令的第一输入（212），解码指令的控制逻辑（402）以及耦合到第一输入（212）和控制逻辑（400）的指令流水线（400）。指令流水线（400）响应于第一信号（214）将获取大小设置为第一大小和第二大小中的一个。因此，数据处理器（202）允许基于所访问设备的特性来改变指令获取策略，以便实现改进的性能。

88. 发明授权

US06401196B1 Data processor system having branch control and method thereof 失效
标题翻译：具有分支控制的数据处理器系统及其方法
公开(公告)号：US06401196B1
公开(公告)日：2002-06-04
申请号：US09100669
申请日：1998-06-19
申请人： Lea Hwang Lee , William C. Moyer , Jeffrey W. Scott , John H. Arends
发明人： Lea Hwang Lee , William C. Moyer , Jeffrey W. Scott , John H. Arends
IPC分类号： G06F912
CPC分类号： G06F9/324 , G06F9/325
摘要： A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.
摘要翻译：公开了在分支地址处取出反向分支地址指令的具体实现。后向分支指令具有一个偏移值，用于定义程序循环的大小。计数器设置为与循环大小成比例的值。在一个示例中，计数器设置为偏移值。当执行循环的每个指令时，计数器被修改以指示循环中剩余的指令数。当循环当前通过中没有指令时，计数器将重置为偏移值，并重复循环直到遇到终止条件。作为实现的一部分，在循环执行之前读取并存储分支指令之后的指令。

89. 发明授权

US6052302A Bit-wise conditional write method and system for an MRAM 有权
标题翻译：用于MRAM的逐位条件写入方法和系统
公开(公告)号：US6052302A
公开(公告)日：2000-04-18
申请号：US406425
申请日：1999-09-27
申请人： William C. Moyer , Jeffrey Van Myers , Noel R. Strader, II
发明人： William C. Moyer , Jeffrey Van Myers , Noel R. Strader, II
IPC分类号： G11C11/16 , G11C11/15
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A bit-wise conditional write method and apparatus to minimize power consumption in integrated circuit (IC) magnetoresistive random access memory (MRAM) systems. In a first embodiment, the current logic state of each data bit of a word stored in the MRAM is compared to a corresponding input bit and only those stored data bits which are different are written. In a second embodiment, for each stored data bit which is not being written, the current logic state is guarded against inadvertent modification when other data bits of the word are written. In a third embodiment, if the logic states of a majority of the stored data bits comprising a word are different from the logic states of the respective input bits, the input bits are first complemented so that less than a majority of the stored data bits actually need to be changed, and a complement bit, appended to each word in the MRAM, is set to indicate that the correct logic states of the stored data bits comprising the respective word must be restored upon subsequent readout.
摘要翻译：用于最小化集成电路（IC）磁阻随机存取存储器（MRAM）系统中的功耗的逐位条件写入方法和装置。在第一实施例中，将存储在MRAM中的字的每个数据位的当前逻辑状态与相应的输入位进行比较，并且仅写入不同的那些存储的数据位。在第二实施例中，对于未被写入的每个存储的数据位，当该字的其它数据位被写入时，当前逻辑状态被防止无意修改。在第三实施例中，如果包括字的所存储的数据位的多数逻辑状态与各个输入位的逻辑状态不同，则首先对输入位进行补码，使得小于存储的数据位的大部分实际上需要改变，并且附加到MRAM中的每个字的补码位被设置为指示随后读出时必须恢复包含相应字的所存储的数据位的正确逻辑状态。

90. 发明授权

US6049876A Data processing system and method which detect unauthorized memory accesses 失效
标题翻译：检测未经授权的内存访问的数据处理系统和方法
公开(公告)号：US6049876A
公开(公告)日：2000-04-11
申请号：US32015
申请日：1998-02-09
申请人： Claude Moughanni , William C. Moyer , Taimur Aslam
发明人： Claude Moughanni , William C. Moyer , Taimur Aslam
IPC分类号： G06F12/14
CPC分类号： G06F12/1441 , G06F12/1433
摘要： A data processing system (10) which detects unauthorized memory accesses has trap door logic (17) that receives memory address bus (16) signals from a processor (12). The trap door logic (12) utilizes address detection logic (50, 52) to identify page numbers utilizing high order address bits and trap regions utilizing low order address bits. The resulting page number (70-76) signals and trap region (41-44) signals are selectively combined (54) to generate an exception signal (18) which is received by security logic (19). The selective combination (54) may be programmed, or may be fixed during fabrication. In response to the exception signal (18), the security logic (19) implements a predefined security policy, which is transmitted to the processor (12) over control lines (20).
摘要翻译：检测未经授权的存储器访问的数据处理系统（10）具有从处理器（12）接收存储器地址总线（16）信号的陷阱门逻辑（17）。陷阱门逻辑（12）利用地址检测逻辑（50,52）来利用利用低阶地址位的高阶地址位和陷阱区来识别页码。选择性地组合（54）所得到的页码（70-76）信号和陷阱区（41-44）信号以产生由安全逻辑（19）接收的异常信号（18）。选择性组合（54）可以被编程，或者可以在制造期间被固定。响应于异常信号（18），安全逻辑（19）实现预定义的安全策略，其通过控制线（20）发送到处理器（12）。

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