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81. 发明申请

US20070051804A1 SECURE VOTING SYSTEM 有权
标题翻译：安全投票制度
公开(公告)号：US20070051804A1
公开(公告)日：2007-03-08
申请号：US11162297
申请日：2005-09-06
申请人： Jay Anderson , Edward Kelley , Franco Motika
发明人： Jay Anderson , Edward Kelley , Franco Motika
IPC分类号： G07C13/00
CPC分类号： G07C13/00
摘要： Methods, systems and program products for securely voting by providing a secure voting module in communication with a voting device. A voter signs onto the voting device using a unique voter identification, and the voter's voting selections are written to the voting device. A scrambled voter identification is generated using the unique voter identification and a unique encryption value of the secure voting module, whereby the voting selections and the scrambled voter identification are stored in the secure voting module. Once voting has ended, first and second fuses are blown within the secure voting module for destroying the unique encryption value and for permanently storing the voting selections and scrambled voter identification in a read only secure voting module that maintains voter anonymity while preventing any further physically writing thereto. The voting results may then be counted, re-counted or validated.
摘要翻译：通过提供与投票设备通信的安全投票模块来安全投票的方法，系统和程序产品。投票人使用独特的选民身份登录投票设备，并将投票人的投票选择写入投票设备。使用独特的选民识别和安全投票模块的唯一加密值来生成加扰的选民识别，由此投票选择和加扰的选民识别被存储在安全投票模块中。一旦投票结束，第一和第二保险丝在安全投票模块内被吹入，以破坏唯一的加密值，并将投票选择和加密的选民识别永久存储在仅保护投票者匿名的只读安全投票模块中，同时防止进一步的物理写入到此。投票结果可能会被计算，重新计算或验证。

82. 发明申请

US20060196929A1 MULTIPLE USE SECURE TRANSACTION CARD 审中-公开
标题翻译：多用途安全交易卡
公开(公告)号：US20060196929A1
公开(公告)日：2006-09-07
申请号：US10906692
申请日：2005-03-02
申请人： Edward Kelley , Franco Motika
发明人： Edward Kelley , Franco Motika
IPC分类号： G06K5/00 , G06K19/06
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/3574 , G06Q20/388 , G06Q20/4014 , G06Q20/40975
摘要： Diverse and or multiple functions are performed in a secure manner using a secure transaction card which validates a holder of the secure transaction card in accordance with a Personal Identification Number (PIN), generates, encrypts and transmits a pair of pseudo-random number sequences through a card reader to validate the card and generates, encrypts and transmits control signals or other information corresponding to a function comprising at least one of personal identity data, passport data, equipment control signals, an entry request to a secure area, medical records or access data therefor, note pad access data and secure telephone entry data in accordance with a protocol suitable for each function. One or more such functions can thus be performed in a secure manner from a single secure transaction card and selection, if needed, can be performed by a menu included in the secure transaction card.
摘要翻译：使用安全交易卡执行不同的或多个功能，该安全交易卡根据个人识别号码（PIN）验证安全交易卡的持有者，通过以下方式产生，加密和发送一对伪随机数序列用于验证所述卡并生成，加密和传输对应于包括个人身份数据，护照数据，设备控制信号，到安全区域的入境请求，医疗记录或访问中的至少一个的功能的控制信号或其他信息数据，便笺本身访问数据和安全电话录入数据，按照适用于每个功能的协议。因此，可以以安全的方式从单个安全交易卡执行一个或多个这样的功能，如果需要，可以通过包括在安全交易卡中的菜单执行选择。

83. 发明申请

US20060195901A1 Integrated System Security Method 失效
标题翻译：集成系统安全方法
公开(公告)号：US20060195901A1
公开(公告)日：2006-08-31
申请号：US11381436
申请日：2006-05-03
申请人： Edward Kelley , Franco Motika , Paul Motika , Eric Motika
发明人： Edward Kelley , Franco Motika , Paul Motika , Eric Motika
IPC分类号： G06F12/14 , H04L9/00 , H04L9/32 , H04K1/00 , G06F12/00 , G06F13/00 , G06F17/30 , G06F7/04 , G06F7/58 , G06K19/00 , G11C7/00
CPC分类号： G06F21/88 , G06F21/31 , G07C9/00142
摘要： Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as computers, appliances, consumer electronics, automobiles, etc. from theft or unauthorized use. Level sensitive scan design (LSSD) techniques are used in conjunction with e-fuses to inhibit or enable system components and sub-components based upon a pre-initialized configuration which must be enabled by a user via password entry.
摘要翻译：基于逻辑扫描的设计和电子熔丝（e-fuse）技术被组合以产生集成在处理器芯片或相关电路的非关键区域中的电路宏功能，以提供保护电子系统和设备的新手段，例如计算机，电器，消费电子，汽车等从盗窃或未经授权的使用。等级敏感扫描设计（LSSD）技术与电子熔丝一起使用，以根据用户通过密码输入启用的预初始化配置来禁止或启用系统组件和子组件。

84. 发明申请

US20060168548A1 GUI POINTER AUTOMATIC POSITION VECTORING 有权
公开(公告)号：US20060168548A1
公开(公告)日：2006-07-27
申请号：US10905853
申请日：2005-01-24
申请人： Edward Kelley , Franco Motika
发明人： Edward Kelley , Franco Motika
IPC分类号： G06F9/00
CPC分类号： G06F3/04812 , G06F3/04842
摘要： A method and computer system for rapid and accurate automatic vectoring of a graphical user interface pointer to a selectable item on a display. Based upon pointer movement input from a pointing device (e.g., a mouse, touchpad or specially configured keyboard), a direction of travel vector from an initial anchor position towards a target item is determined. The location of the target item is extrapolated and the pointer is automatically moved to that target item. To ensure that the pointer moves to the intended target item, the location of the target item is extrapolated based upon the direction of travel vector and default and/or user defined parameters. Optional user defined parameters include initial pointer anchor position, vector sensitivity, automatic selection of target item, and user defined pointer limitations.

85. 发明申请

US20060157553A1 ACCOMMODATING MULTIPLE USERS OF A SECURE CREDIT CARD 审中-公开
标题翻译：存储安全信用卡的多个用户
公开(公告)号：US20060157553A1
公开(公告)日：2006-07-20
申请号：US10905716
申请日：2005-01-18
申请人： Edward Kelley , Franco Motika
发明人： Edward Kelley , Franco Motika
IPC分类号： G06K5/00 , G06K19/06 , G06Q40/00 , G06Q20/00
CPC分类号： G07F7/1008 , G06Q20/206 , G06Q20/3555 , G06Q20/40 , G07F7/1025
摘要： A secure credit card provides for secure transactions by users other than a holder of the secure credit card by providing storage for additional personal identification numbers (PINs) for authorized users. Transactions for authorized users may be controlled in accordance with individual user profiles stored in the secure credit card and which may be freely and flexibly established in regard to transaction amount, merchant restrictions and the like in response to recognition of a PIN corresponding to a holder of the secure credit card to whom the card is issued.
摘要翻译：一个安全的信用卡通过为授权的用户提供额外的个人识别号码（PIN）来提供安全信用卡持有者以外的用户的安全交易。授权用户的交易可以根据存储在安全信用卡中的个人用户简档进行控制，并且可以响应于对应于对应于持有者的PIN的识别而关于交易金额，商家限制等自由地和灵活地建立交易发卡卡的安全信用卡。

86. 发明申请

US20050188290A1 Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic 失效
标题翻译：基于皮秒成像 - 电路分析的内置自检诊断方法和结构
公开(公告)号：US20050188290A1
公开(公告)日：2005-08-25
申请号：US10780878
申请日：2004-02-19
申请人： Franco Motika , Peilin Song
发明人： Franco Motika , Peilin Song
IPC分类号： G01R31/28 , G01R31/311 , G01R31/3185
CPC分类号： G01R31/318547 , G01R31/311
摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.
摘要翻译：测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环通过电路的预定操作周期。

87. 发明申请

US20050138501A1 System and method for testing electronic devices on a microchip 失效
标题翻译：在微芯片上测试电子设备的系统和方法
公开(公告)号：US20050138501A1
公开(公告)日：2005-06-23
申请号：US10721646
申请日：2003-11-25
申请人： Franco Motika , William Huott
发明人： Franco Motika , William Huott
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G11C29/40
CPC分类号： G01R31/318566 , G01R31/31703 , G11C29/40
摘要： A system and method for testing first and second sets of electronic devices on a microchip is provided. The first set of devices receive input data and then send output data to a first multiple input shift register (MISR). The second set of devices receiving input data and then sending output data to a second MISR. The method includes determining a first seed signature value associated with the first MISR that induces the first MISR to have a first final signature value comprising a plurality of identical binary values when the first set of devices send valid output data to the first MISR when receiving a first predetermined sequence of input data. The method further includes determining a second seed signature value associated with the second MISR that induces the second MISR to have a second final signature value comprising a plurality of identical binary values when the second set of devices send valid output data to the second MISR when receiving a second predetermined sequence of input data. The method further includes initializing first and second states of the first MISR and the second MISR, respectively, to the first and second signature values, respectively. The method further includes inputting the first and second predetermined sequences of input data to the first and second set of devices, respectively, and generating first and second final signatures values from output data received from the first and second set of devices, respectively. Finally, the method includes indicating that the first and second set of devices have failed testing when at least one of the plurality of binary values in the first and second final signature values are not identical.
摘要翻译：提供了一种用于在微芯片上测试第一和第二组电子设备的系统和方法。第一组设备接收输入数据，然后将输出数据发送到第一个多输入移位寄存器（MISR）。第二组设备接收输入数据，然后将输出数据发送到第二MISR。该方法包括：当第一组设备在接收到第一MISR时向第一MISR发送有效输出数据时，确定与第一MISR相关联的第一种子签名值，该第一种子签名值诱导第一MISR具有包括多个相同二进制值的第一最终签名值第一预定的输入数据序列。所述方法还包括：当所述第二组设备在接收到所述第二MISR时向第二MISR发送有效输出数据时，确定与所述第二MISR相关联的第二种子签名值，所述第二种子签名值诱导所述第二MISR具有包括多个相同二进制值的第二最终签名值输入数据的第二预定序列。该方法还包括分别将第一MISR和第二MISR的第一和第二状态初始化到第一和第二签名值。该方法还包括分别将输入数据的第一和第二预定序列输入到第一和第二组设备，并分别从从第一和第二组设备接收的输出数据产生第一和第二最终签名值。最后，该方法包括当第一和第二最终签名值中的多个二进制值中的至少一个不相同时，指示第一和第二组设备具有失败的测试。

88. 发明授权

US06865501B2 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 失效
公开(公告)号：US06865501B2
公开(公告)日：2005-03-08
申请号：US10697365
申请日：2003-10-30
申请人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
发明人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
IPC分类号： G01R31/319 , G01R31/3193 , G06F19/00
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

89. 发明授权

US06816990B2 VLSI chip test power reduction 失效
标题翻译： VLSI芯片测试功耗降低
公开(公告)号：US06816990B2
公开(公告)日：2004-11-09
申请号：US10058485
申请日：2002-01-28
申请人： Peilin Song , Timothy J. Koprowski , Ulrich Baur , Franco Motika
发明人： Peilin Song , Timothy J. Koprowski , Ulrich Baur , Franco Motika
IPC分类号： G01R3128
CPC分类号： G01R31/31721 , G01R31/31707 , G01R31/318307 , G01R31/318502 , G01R31/318522 , G01R31/3187
摘要： LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.
摘要翻译： LBIST和加权LBIST测试在测试对象的不同部分上同时进行。这种新的测试方法和设计变化与传统的测试策略相比，测试覆盖率和测试时间都大大降低。它可以应用于晶圆，芯片，MCM和系统测试级别。最重要的是，它不需要新的支持工具。当前的测试软件将与传统的测试策略一样工作。在相同测试会话中调度LBIST和加权LBIST测试降低了整体功耗，因为加权LBIST测试比平面LBIST测试消耗的功率少得多。在相同的测试会话中，如果使用加权LBIST测试逻辑的某些部分，而使用LBIST测试其他部分，则电路元件在任何给定时间消耗的功率降低。

90. 发明授权

US06327685B1 Logic built-in self test 有权
标题翻译：逻辑内置自检
公开(公告)号：US06327685B1
公开(公告)日：2001-12-04
申请号：US09310444
申请日：1999-05-12
申请人： Timothy J. Koprowski , Franco Motika
发明人： Timothy J. Koprowski , Franco Motika
IPC分类号： G01R3128
CPC分类号： G01R31/3181
摘要： A BIST method that modifies the scan chain path and scan clocks to allow for distributed BIST test. In this distributed BIST concept, the Linear Feedback Shift Register (LFSR) and the Multiple Input Signature Register (MISR) are combined as an integral part of the scan chain, and each scan cycle is utilized as a test cycle.
摘要翻译： BIST方法修改扫描链路和扫描时钟以允许分布式BIST测试。在这种分布式BIST概念中，线性反馈移位寄存器（LFSR）和多输入签名寄存器（MISR）被组合为扫描链的组成部分，并且每个扫描周期被用作测试周期。

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