专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080098268A1 USING CLOCK GATING OR SIGNAL GATING TO PARTITION A DEVICE FOR FAULT ISOLATION AND DIAGNOSTIC DATA COLLECTION 审中-公开
标题翻译：使用时钟增益或信号增益分割故障分离和诊断数据收集的设备
公开(公告)号：US20080098268A1
公开(公告)日：2008-04-24
申请号：US11933385
申请日：2007-10-31
申请人： Leendert Huisman , William Huott , Franco Motika , Leah Pfeifer Pastel
发明人： Leendert Huisman , William Huott , Franco Motika , Leah Pfeifer Pastel
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.
摘要翻译：在一个方面，测试了通过使用时钟门控或信号门控被划分成段的电子设备。识别出作为故障来源的细分之一。将诊断程序应用于识别的段以确定故障的原因。

2. 发明申请

US20050193297A1 METHODS AND APPARATUS FOR DEFECT ISOLATION 失效
标题翻译：缺陷分离方法与装置
公开(公告)号：US20050193297A1
公开(公告)日：2005-09-01
申请号：US10708380
申请日：2004-02-27
申请人： Leendert Huisman , William Huott , Maroun Kassab , Franco Motika
发明人： Leendert Huisman , William Huott , Maroun Kassab , Franco Motika
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318533
摘要： In a first aspect, a first method is provided for isolating a defect in a scan chain. The first method includes the steps of (1) modifying a first test mode of one or more of a plurality of latches included in the scan chain; (2) operating the one or more latches whose first test modes are modified in the modified first test mode; and (3) operating one or more of the plurality of latches included in the scan chain in a second test mode. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了用于隔离扫描链中的缺陷的第一方法。第一种方法包括以下步骤：（1）修改包括在扫描链中的多个锁存器中的一个或多个的第一测试模式; （2）在修改后的第一测试模式下操作其第一测试模式被修改的一个或多个锁存器; 以及（3）在第二测试模式中操作包括在扫描链中的多个锁存器中的一个或多个。提供了许多其他方面。

3. 发明申请

US20050108599A1 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 有权
标题翻译：使用时钟门控或信号门控对设备进行分区以进行故障隔离和诊断数据采集
公开(公告)号：US20050108599A1
公开(公告)日：2005-05-19
申请号：US11006274
申请日：2004-12-07
申请人： Leendert Huisman , William Huott , Franco Motika , Leah Pfeifer Pastel
发明人： Leendert Huisman , William Huott , Franco Motika , Leah Pfeifer Pastel
IPC分类号： G01R31/319 , G01R31/3193 , G11B20/20 , G06F7/50 , G06K5/04 , G11B5/00
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.
摘要翻译：在一个方面，测试了通过使用时钟门控或信号门控被划分成段的电子设备。识别出作为故障来源的细分之一。将诊断程序应用于识别的段以确定故障的原因。

4. 发明申请

US20080059857A1 METHODS AND APPARATUS FOR TESTING A SCAN CHAIN TO ISOLATE DEFECTS 失效
标题翻译：用于测试扫描链以分离缺陷的方法和装置
公开(公告)号：US20080059857A1
公开(公告)日：2008-03-06
申请号：US11924597
申请日：2007-10-25
申请人： LEENDERT HUISMAN , William Huott , Maroun Kassab , Franco Motika
发明人： LEENDERT HUISMAN , William Huott , Maroun Kassab , Franco Motika
IPC分类号： G01R31/28
CPC分类号： G01R31/318533
摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.
摘要翻译：提供了用于隔离扫描链中的缺陷的系统，方法和装置。本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值，到了错误。这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。提供了许多其他方面。

5. 发明申请

US20050138501A1 System and method for testing electronic devices on a microchip 失效
标题翻译：在微芯片上测试电子设备的系统和方法
公开(公告)号：US20050138501A1
公开(公告)日：2005-06-23
申请号：US10721646
申请日：2003-11-25
申请人： Franco Motika , William Huott
发明人： Franco Motika , William Huott
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G11C29/40
CPC分类号： G01R31/318566 , G01R31/31703 , G11C29/40
摘要： A system and method for testing first and second sets of electronic devices on a microchip is provided. The first set of devices receive input data and then send output data to a first multiple input shift register (MISR). The second set of devices receiving input data and then sending output data to a second MISR. The method includes determining a first seed signature value associated with the first MISR that induces the first MISR to have a first final signature value comprising a plurality of identical binary values when the first set of devices send valid output data to the first MISR when receiving a first predetermined sequence of input data. The method further includes determining a second seed signature value associated with the second MISR that induces the second MISR to have a second final signature value comprising a plurality of identical binary values when the second set of devices send valid output data to the second MISR when receiving a second predetermined sequence of input data. The method further includes initializing first and second states of the first MISR and the second MISR, respectively, to the first and second signature values, respectively. The method further includes inputting the first and second predetermined sequences of input data to the first and second set of devices, respectively, and generating first and second final signatures values from output data received from the first and second set of devices, respectively. Finally, the method includes indicating that the first and second set of devices have failed testing when at least one of the plurality of binary values in the first and second final signature values are not identical.
摘要翻译：提供了一种用于在微芯片上测试第一和第二组电子设备的系统和方法。第一组设备接收输入数据，然后将输出数据发送到第一个多输入移位寄存器（MISR）。第二组设备接收输入数据，然后将输出数据发送到第二MISR。该方法包括：当第一组设备在接收到第一MISR时向第一MISR发送有效输出数据时，确定与第一MISR相关联的第一种子签名值，该第一种子签名值诱导第一MISR具有包括多个相同二进制值的第一最终签名值第一预定的输入数据序列。所述方法还包括：当所述第二组设备在接收到所述第二MISR时向第二MISR发送有效输出数据时，确定与所述第二MISR相关联的第二种子签名值，所述第二种子签名值诱导所述第二MISR具有包括多个相同二进制值的第二最终签名值输入数据的第二预定序列。该方法还包括分别将第一MISR和第二MISR的第一和第二状态初始化到第一和第二签名值。该方法还包括分别将输入数据的第一和第二预定序列输入到第一和第二组设备，并分别从从第一和第二组设备接收的输出数据产生第一和第二最终签名值。最后，该方法包括当第一和第二最终签名值中的多个二进制值中的至少一个不相同时，指示第一和第二组设备具有失败的测试。

6. 发明申请

US20060174175A1 Array self repair using built-in self test techniques 失效
标题翻译：使用内置自检技术进行阵列自修复
公开(公告)号：US20060174175A1
公开(公告)日：2006-08-03
申请号：US11047419
申请日：2005-01-31
申请人： William Huott , Franco Motika , Pradip Patel , Daniel Rodko
发明人： William Huott , Franco Motika , Pradip Patel , Daniel Rodko
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318566
摘要： A soft-fuse test algorithm is distributed on-chip from an ABIST engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Each arrays outputs are monitored by a different multiple input signature register (MISR) with an initial data pattern seed that provides a final desired state of the MISR with either all “0”s or all “1”s, allowing for a simple “single-bit” MISR error evaluation of the monitored array. Using the above single-bit MISR error evaluation technique an ABIST test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.
摘要翻译：软保险丝测试算法通过LSSD移位寄存器链从ABIST引擎分布在片上，以动态评估多个阵列，对坏元素进行冗余补偿，并修复可修复的阵列。每个阵列输出由具有初始数据模式种子的不同的多输入签名寄存器（MISR）监视，提供MISR的所有“0”或全“1”的最终期望状态，允许简单的“单 -bit“监控阵列的MISR错误评估。使用上述单位MISR错误评估技术，通过移位寄存器链在所有阵列上同时执行ABIST测试序列。如果任何阵列出现错误，则采用冗余补偿，并对所有可能的阵列冗余组合重复ABIST测试，直到每个阵列的功能配置被识别或已尝试所有可能的冗余组合。一旦功能阵列配置被验证，相关联的软保险丝状态可以用于熔断和/或提取用于进一步的系统设置，永久保险丝熔断和产量分析。可能需要由单独的ABIST引擎驱动的多个移位寄存器链来测试芯片上的所有阵列。

7. 发明授权

US08055587B2 Man in the middle computer technique 失效
标题翻译：人在中间计算机技术
公开(公告)号：US08055587B2
公开(公告)日：2011-11-08
申请号：US12132203
申请日：2008-06-03
申请人： Wayne M. Delia , Edward E. Kelley , Franco Motika
发明人： Wayne M. Delia , Edward E. Kelley , Franco Motika
IPC分类号： H04L9/32 , G06F17/60
CPC分类号： H04L63/0428 , H04L63/083 , H04L63/1466
摘要： A method for constructing a secure Internet transaction, the method includes: receiving a user identification (userid) and user password on a client device for filling out a form generated by a secure web site; concatenating the user's Internet Protocol (IP) address with a separate password that is maintained on the secure web site that the user is authenticating to; encrypting the concatenated user IP and separate password to form an Internet Protocol password (IPPW); wherein the encrypting is carried out with a client device linear feedback shift register (LFSR) with a defined cycle count; building a transaction consisting of the IPPW, defined cycle count, and userid; transmitting the transaction and form via a network towards the secure web site; wherein in response the secure website performs the following: decrypts the IPPW, and determines if the IP portion of the decrypted IPPW is equal to the user's IP address.
摘要翻译：一种用于构建安全因特网事务的方法，所述方法包括：在客户端设备上接收用户标识（用户ID）和用户密码，以填写由安全网站生成的表单; 将用户的因特网协议（IP）地址与在用户正在认证的安全网站上维护的单独的密码连接起来; 加密连接的用户IP和单独的密码以形成Internet协议密码（IPPW）; 其中所述加密是利用具有定义的周期计数的客户端设备线性反馈移位寄存器（LFSR）来执行的; 构建由IPPW，定义的循环计数和userid组成的事务; 通过网络向安全网站传送交易和表单; 其中作为响应，安全网站执行以下操作：解密IPPW，并确定解密的IPPW的IP部分是否等于用户的IP地址。

8. 发明授权

US08050484B2 Method and system for image recognition for aiding the visually impaired 失效
标题翻译：帮助视力障碍者进行图像识别的方法和系统
公开(公告)号：US08050484B2
公开(公告)日：2011-11-01
申请号：US11833547
申请日：2007-08-03
申请人： Joseph B. Frei , Edward E. Kelley , Franco Motika
发明人： Joseph B. Frei , Edward E. Kelley , Franco Motika
IPC分类号： G06K9/00
CPC分类号： G09B21/003
摘要： A method for tracking paper currency in a holder, includes: scanning paper currency deposited or removed from a holder; determining the total number of each individual denomination of paper currency contained within the holder based on the scanned paper currency deposited and removed from the holder; recording the total number of each individual denomination of paper currency; determining the total value of the paper currency within the holder; outputting the denomination of paper currency when the paper currency is scanned during depositing or removal from the holder; outputting the recorded number of each individual denomination of paper currency and the total value of the currency within the holder; and wherein the recorded number of each individual denomination of paper currency and the total value of the currency within the holder is dynamically tabulated based on the scanning of paper currency deposited or removed from the holder.
摘要翻译：用于跟踪持有人纸币的方法包括：扫描从持有人存放或移走的纸币; 根据从持有人存放和移除的扫描纸币确定持有人所包含的每种纸币种类总数; 记录每个单位面值纸币的总数; 确定持有人内纸币的总价值; 在从持有人进行存放或清除期间扫描纸币时输出纸币的面额; 输出每个单独面值纸币的记录数量和持有人内货币的总价值; 并且其中，基于从所述持有者存放或移除的纸币的扫描，将所述纸币的每个单独面值的记录数量和所述持有者内的所述货币的总价值动态地列表。

9. 发明授权

US07759960B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07759960B2
公开(公告)日：2010-07-20
申请号：US12103906
申请日：2008-04-16
申请人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

10. 发明申请

US20100146606A1 AUTHENTICATION METHOD AND SYSTEM 失效
标题翻译：认证方法与系统
公开(公告)号：US20100146606A1
公开(公告)日：2010-06-10
申请号：US12329229
申请日：2008-12-05
申请人： Wayne Michael Delia , Edward Emile Kelley , Franco Motika
发明人： Wayne Michael Delia , Edward Emile Kelley , Franco Motika
IPC分类号： H04L9/32
CPC分类号： G06F21/32
摘要： An authentication method and system. A computing system generates an authentication table associated with a user. The computing system receives first authentication data and second authentication data differing from the first authentication data. The first authentication data and the second authentication data are placed in the authentication table. The authentication table comprising the first authentication data and the second authentication data is stored in the computing system. The computing system generates an action table. The computing system receives first action data and second action data and places the first action data and the second action data in the action table. The action table comprising the first action data and the second action data is stored in the computing system.
摘要翻译：一种认证方法和系统。计算系统生成与用户相关联的认证表。计算系统接收与第一认证数据不同的第一认证数据和第二认证数据。第一认证数据和第二认证数据被放置在认证表中。包括第一认证数据和第二认证数据的认证表被存储在计算系统中。计算系统生成一个动作表。计算系统接收第一动作数据和第二动作数据，并将动作数据和第二动作数据放置在动作表中。包括第一动作数据和第二动作数据的动作表被存储在计算系统中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式